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My main references are the Berkhout papers (eg. Audio at Low and High Power) and also "A 700+-mW Class D Design With Direct Battery Hookup in a 90-nm Process" (Forejt, et al), which is the paper I'm working from (but with low voltage P/N output). They show their integrator circuit, but not the...
I have two problems, one practical, one conceptual.
The practical problem is that I need to design an integrator for a 384kHz PWM Class-D system, but I'm not sure of how to derive specifications for the integrator.
This leads to the second, conceptual, problem: how do practical integrator...
It's for a Class-D system, ie:
However, I'm only simulating the integrator on its own at the moment, I'm trying to understand what the important specifications of the integrator are, and so how to choose them. So the linearity in the first post is the linearity of the integrator ie. I apply a...
Hi,
How does integrator phase error affect performance of an integrator? I've read that typically we aim for 1-2 degrees phase error around the frequency of interest, but why?
Using a model of a two pole structure (integration pole plus high frequency transconductor pole - ie. a gm-c...
I'm not sure exactly what this circuit does, but in general you might have a power control register (eg. a chain of d-type flip flops, so that you can clock data in to the first flipflop serially, and read out in parallel, as eg. PD0-2 bits). The state of each D-type defines whether the block...
I not sure exactly, but perhaps keep in mind definition of Vt (eg. section 3.1), Vt = Vt0 + f(Vsb), a function of source-bulk voltage. So VT03 refers to threshold voltage of M3 which has source-bulk connected (so Vt == Vt0), whereas M1 hasn't got bulk-source connected and so Vt1 depends on Vin...
46.6x oversampling because want 100db attenuation of switching harmonic. Using 3rd order class-D output filter (60dB/dec), so -100dB is at 17.81MHz == 46.6 * 384khz.
maxstep=25ns gives -60db noise floor. I think that strobeperiod is the same as maxstep? maxstep sets max simulation step...
Sigma delta has other advantages - eg. use with Class-D output stage for good power efficiency, or "easy" to implement high linearity (with enough oversampling/noise shaping) in single-bit systems, as single comparator has no non-linearity (only gain error).
Can measure output power by integrating the power across the load (after output filter) and dividing by integration period according to E=integral(P)/t=integral(IV)/t (eg. integ(V("/OUT")*I("/R0/PLUS") 0 1e-3 ))/1e-3), or using rms to calculate (eg. rms(V("/OUT"))**2/rload). With single supply...
Hi, how to get a clean FFT in Class-D simulation? I start from ideal model and want to slowly build in non-idealities and see the effect on Class-D performance. So with simple 384khz PWM Class-D with third order output filter, I aim for aliasing below -100dB (so can see all distortions greater...
Hi, I try to design integrator but a bit confused about how to go from high level design (unity gain frequency, DC gain) to low level design. Using a gm-c structure, but what current do I use in the gm stage? unity-gain frequency is independent of current (can scale Gm and C at the same time)...
Think I understand this now, after stumbling across answer in a book*. Just in case anyone else is having the same problem, here's the answer.
(Paraphrased:) "Applying linear system concepts to a sigma delta provides valuable insight, but is flawed from the outset", presumably as the sigma...
Hi,
I try to match model of first order sigma delta to spectre simulation results, but they disagree!
First figure attached is first order sigma-delta model (comparator shown as a summing node and noise source N(s)). Can solve to get:
Y = N/(1+H) + H*X/(1+H) where H=K/s
So if K/s >> 1...
Hi, please see attached op-amp testbench.
I need 10MHz GBW, so I have got this in unity gain configuration (ie. output shorted to input, Rfb=0). I used a +/- 1.0V DC sources in place of the Rfb to make sure the output is at maximum slew, where because of reduced Vds over current sources, they...
To give an idea of what is happening, here are measured results from simulation:
Vin Rin Rfb GBW Av0(dB) fpole(Hz) gm GBW_CL
------------------------------------------------------------------------
2.0 1k 0 10.8M 86.125 353.8 70.42u
2.0 1k...
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