Power Down Circuit - Explanation

[laiza]

Hello EDA,

Can anyone explain to me how this PD (Power down circuit) works?
What is a Power Down Register , what it comprises? are they comprise of flipflops?


Thanks.

 

[ansu_s]

I'm not sure exactly what this circuit does, but in general you might have a power control register (eg. a chain of d-type flip flops, so that you can clock data in to the first flipflop serially, and read out in parallel, as eg. PD0-2 bits). The state of each D-type defines whether the block controlled by that bit is enabled or disabled. Perhaps you also have a hardware powerdown switch/pin in your chip/circuit (eg. the PDN signal), and maybe something to detect brownouts, a microcontroller or something, which might generate eg. a TFAULT signal when it detects the supply dropping.

Then you might also need some logic to control take these input signals (PD0-2, TFAULT, PDN) and do something sensible with them, like powering-up and powering down your analog and digital blocks in the correct sequence, as sometimes if you powerup your blocks in the wrong order, circuits may not start up properly or if you powerdown in the wrong order, you can cause damage.