integrator design, phase error

[ansu_s]

Hi,

How does integrator phase error affect performance of an integrator? I've read that typically we aim for 1-2 degrees phase error around the frequency of interest, but why?

Using a model of a two pole structure (integration pole plus high frequency transconductor pole - ie. a gm-c integrator structure), I looked at the linearity of the integrator over frequency and plotted the phase error (-90 degrees minus the phase shift at that frequency, versus the ratio of first to third harmonic, in db):


So around 0 degrees phase error (ie. 90 degree integrator phase shift), linearity is better. Is this why we want to minimise phase shift, to improve linearity? But then, looking closely at the plot, linearity is actually highest when phase error is +4 degrees - why does this give greatest linearity and not 0 degrees phase error?

Some have said that reducing phase error affects the Q of the system - but isn't Q how damped the system is? Why does an integrator care about Q? Is this something to do with how lossy the integrator is? If so, wouldn't this affect the DC gain, not the linearity?

For background: I'm trying to design an integrator for an audio Class-D amplifier, but I'm not sure about how to specify the integrator. Also, if it's important, the magnitude/phase of the integrator is shown below (I just picked the two pole frequencies to give me good a good range of points to investigate effect of phase error on linearity).

 

[FvM]

You're telling assumptions about the relation between integrator properties and a class-D design without showing a system diagram. Don't expect answers on this.

I won't consider the bode plot as an integrator characteristic. It could be the open loop gain of some high speed OP as well. For an integrator, one would expect at least a 90° phase plateau.

 

[ansu_s]

It's for a Class-D system, ie:


However, I'm only simulating the integrator on its own at the moment, I'm trying to understand what the important specifications of the integrator are, and so how to choose them. So the linearity in the first post is the linearity of the integrator ie. I apply a sinewave to the integrator input, and FFT the integrator output.

I've moved the integrator poles so that there is a phase plateau:


and I've looked at the linearity at a range of tone frequencies, again plotting phase error (=-90 - phase shift) vs magnitude of the first harmonic minus magnitude of the third (dominant) harmonic), and I get the same behavior - large negative phase error gives poor linearity, phase error around 0 degrees is good, but linearity still improves a little for positive phase errors (ie. going higher in frequency, where integrator phase shift becomes greater than 90 degrees). I can't look at higher frequencies/phase shifts as the harmonic is below my FFT noise floor.


I don't quite understand how to determine my allowable phase error - it looks like I need it to be low, but I don't really understand why, or whether there is a way to analytically determine how low it must be.

---------- Post added at 15:19 ---------- Previous post was at 15:05 ----------

Actually, I think my integrator was clipping at low frequencies (which have a large, negative phase error), hence the discontinuity in the graph near 0 degrees phase shift, after this point the integrator stops clipping. So maybe all the above is wrong? This makes me event more lost.

 

[LvW]

Hi ansu_s,

excuse me, but your contributions are somewhat confusing.
Sometimes you speak about phase errors (as a result from a small signal ac analysis) and later on linearity and signal clipping.
Both effects (phase error, linearity, clipping) have no direct relationships!
You should know, that each analog integrator circuit has the exact phase shift of 90 deg. at one frequency only!
Around this "ideal" frequency there is always a phase error.
But that's not surprising since there is no active circuit with ideal properties.
The consequences of such an error (and its maximum allowable value) can be evaluated only in connection with a certain application.
Please, tell us about your real problem.

 

[FvM]

The first missing link may be an explanation, why an ideal integrator should be used in the class-D feedback loop?
The second would be an analysis of error terms, why a phase error should involve harmonic distortion.

Besides all confusing details, these points are far from being obvious, I think.

 

[ansu_s]

I have two problems, one practical, one conceptual.

The practical problem is that I need to design an integrator for a 384kHz PWM Class-D system, but I'm not sure of how to derive specifications for the integrator.

This leads to the second, conceptual, problem: how do practical integrator effects alter the time domain response of the integrator. Clippling is fairly straight forward (ie. just don't clip to maintain linearity). But as you say, the integrator is only an ideal integrator at a single frequency so at other frequencies, what is it doing?

My thinking is that ideally it gives -20dB/dec and 90 degrees phase shift but practically the rate of rolloff could be less at low freq (near the pole) and greater at higher freq (nearer amplifier pole), similar with phase shift. So in an audio signal with multiple frequency components, all (except the ideal one) frequency components get a different magnitude and phase shift to their ideal, which results in some sort of distortion. So to limit the distortion, I think I need to limit the integrator phase shift.

So my second, conceptual, problem is understanding the effect of this integrator non-ideality, and working out what is an acceptable limit on phase error and rate-of-rolloff error.

 

[FvM]

So, do you have any literature links founding the basical design? As another question, did you consider the effects of using natural sampling (e.g. versus regular sampling) for the PWM modulator?

 

[ansu_s]

My main references are the Berkhout papers (eg. Audio at Low and High Power) and also "A 700+-mW Class D Design With Direct Battery Hookup in a 90-nm Process" (Forejt, et al), which is the paper I'm working from (but with low voltage P/N output). They show their integrator circuit, but not the specifications used in the integrator - I haven't found much on the actual design of the internal components.

Also, from the Neilsen AES paper ("A review and comparison of pulse width modulation (PWM) methods for analog and digital input switching power amplifiers"), it looks like natural sampling has less distortion than uniform sampling (no time quantization) and I think the main advantage of uniform sampling would be to interface with a digitally-derived input source, which I don't have, so I'm happy to use natural sampling.

How would I do an analysis of the error terms? Where would I start?

 

[FvM]

I found also some other interesting papers on the B&O publication page besides the said Nielsen AES paper
**broken link removed**

The said Berkhout paper misses a foundation of using an integrator in the closed loop PWM topology or even an analysis of it's behaviour in my opinion.


I don't have the Forejt paper, you should determine, if it gives an analysis of the feedback loop with integrator.

My assumption is, that it has been simply choosen because it's the most simple feedback loop controller. I can't imagine, how you should know about an optimal feedback controller and expectable closed loop performance without specifying the error terms located in the class-D power stage. What kind of non-ideal behaviour is assumed in your simulation? On the other hand, with an ideal output stage, you don't need a closed loop.