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Stacked vias or a single via with multiple rows and columns, which one is a better choice in RFIC applications?
For example, when directing signal from metal layer 6 to 1, using stacked vias is better or single vias with multiple rows and columns (by drawing tracks of different metal to reach...
Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s
I have psub and psub2 layer but no pin layer can be assigned to this layer. for M1(draw), Metal layer1, there is M1(pin) So I would miss one pin (in layout there is only 2 pins while in schematic there is 3). :(
Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s
yes, now I have a 3 terminal NFET. I renamed it to psub but the same error :(
Conflicting connections STAMPing layer sub:2 by layer psub.
Location: (3.600,5.900)
Nets: psub 6
Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s
Thank you erikl for your comment.
I connected the bulk terminal to the source in both schematic and layout but the problem still exists.
TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer sub)
I have drawn a simple NMOS_RF as shown in schematic (I'm using TSMC 0.18 um process).
The layout of the circuit is :
LVS results:
When I check the LVS. I got the following error:
LVS report...
I have centos 6.4 (x64) and virtuoso 6.14 I.
when executing ./iscape.sh in terminal to load iscape.04.21-P004
I got the following error.
some Thing Wrong?
I tried yum install java and yum install glibc.i386 but the problem still exists.
cadence problem: NCSU library with No instance
I have "NCSU library" for cadence. When I want to put an instance in schematic window from any library except "NCSU_Analog_Parts" and "NCSU_Digital_Parts", I have nothing.
For example by changing library to "NCSU_TechLib_ami06", I have this list...
I'm going to design a PA for 4 to 10 GHz band. But the required transistor given for design is Mitsubishi MGF2116 which is not available. What is its equivalent?
Anybody has any idea?
How to determine the minimum width of metal layer for handling a given current in a specific CMOS technology?
If I want to handle 2mA, how to determine the width of metal?
Hi everybody,
I assume I'm using CMOS technology and I want to design a passive inductor.
1. Do I have to last metal for designing an integrated inductor? if my process has got 8 metal layers, then I have to use metal layer 7 and 8?
2.How can I quickly design an inductor for cadence for...
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