TSMC tech RF_NMOS layout problem in LVS

[amir88]

TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer sub)

I have drawn a simple NMOS_RF as shown in schematic (I'm using TSMC 0.18 um process).



The layout of the circuit is :



LVS results:







When I check the LVS. I got the following error:

LVS report:
Conflicting connections STAMPing layer sub:2 by layer psub.

Location: (2.900,6.500)
Nets: myB 7

What's the problem? How can I solve it?

 

[erikl]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

When I check the LVS. I got the following error:

LVS report:

Conflicting connections STAMPing layer sub:2 by layer psub.

Location: (2.900,6.500)
Nets: myB 7

What's the problem? How can I solve it?

I guess you cannot name your bulk connection "myB" - because it is electrically connected to psub - as long as your NFET isn't in a p-bulk island within an isolating NWell.

 

[amir88]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

I guess you cannot name your bulk connection "myB" - because it is electrically connected to psub - as long as your NFET isn't in a p-bulk island within an isolating NWell.

Thank you erikl for your comment.
I connected the bulk terminal to the source in both schematic and layout but the problem still exists.

 

[erikl]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

I connected the bulk terminal to the source in both schematic and layout but the problem still exists.

So you have now a 3-terminal NFET in both schematic and layout? In this case it could be necessary to name the source psub - because it's still electrically connected to it.

 

[amir88]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

So you have now a 3-terminal NFET in both schematic and layout? In this case it could be necessary to name the source psub - because it's still electrically connected to it.

yes, now I have a 3 terminal NFET. I renamed it to psub but the same error


Conflicting connections STAMPing layer sub:2 by layer psub.

Location: (3.600,5.900)
Nets: psub 6

 

[erikl]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

yes, now I have a 3 terminal NFET. I renamed it to psub but the same error

Conflicting connections STAMPing layer sub: ---------------- 2 by layer psub.

Location: (3.600,5.900)
Nets: psub 6

Perhaps the right layer name is sub, not psub - I'm just guessing.

You should see the name of the layer in your LSW.

Try and find a clue at the above mentioned location.

 

[amir88]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

Perhaps the right layer name is sub, not psub - I'm just guessing.

You should see the name of the layer in your LSW.

Try and find a clue at the above mentioned location.

I have psub and psub2 layer but no pin layer can be assigned to this layer. for M1(draw), Metal layer1, there is M1(pin) So I would miss one pin (in layout there is only 2 pins while in schematic there is 3).

 

[rangermad]

I am not familiar with the process and it is hard to tell from the picture. Is the nmos inside a deep nwell? Also, did you highlight net 7?

LVS report:
Conflicting connections STAMPing layer sub:2 by layer psub.

Location: (2.900,6.500)
Nets: myB 7

 

[amir88]

thanks rangermad

 

[erikl]

Re: TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer s

I have psub and psub2 layer but no pin layer can be assigned to this layer. for M1(draw), Metal layer1, there is M1(pin) So I would miss one pin (in layout there is only 2 pins while in schematic there is 3).

Pin layer and pin name are different things: on M1 always use an M1 pin (i.e: M1 pin layer), but its name is arbitrary. I just guessed that its bulk(=source) name should read like sub or psub, because it's connected to it. But I'm not at all sure of this.