amir88
Advanced Member level 4
- Joined
- Nov 4, 2009
- Messages
- 118
- Helped
- 13
- Reputation
- 26
- Reaction score
- 8
- Trophy points
- 1,298
- Location
- bandarabbas
- Activity points
- 1,926
TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer sub)
I have drawn a simple NMOS_RF as shown in schematic (I'm using TSMC 0.18 um process).
The layout of the circuit is :
LVS results:
When I check the LVS. I got the following error:
LVS report:
Conflicting connections STAMPing layer sub:2 by layer psub.
Location: (2.900,6.500)
Nets: myB 7
What's the problem? How can I solve it?
I have drawn a simple NMOS_RF as shown in schematic (I'm using TSMC 0.18 um process).
The layout of the circuit is :
LVS results:
When I check the LVS. I got the following error:
LVS report:
Conflicting connections STAMPing layer sub:2 by layer psub.
Location: (2.900,6.500)
Nets: myB 7
What's the problem? How can I solve it?