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Recent content by amaccormack

  1. A

    why RTL simulation is slow?

    Becuase hardware accelleration only works on gate-level netlists it cannot be used for RTL (unless you synthesise it, obviously, but then its gate-level anyway). Therefore RTL simualtion always has to be in software. But if you simulate gate-level in software, it will be slower than RTL.
  2. A

    How to finish perfect verification?

    Its quite easy to get perfect verification. First get a Cold Fusion power generator, and attatch it to a perpetual motion machine. Then take a philosopher's stone and dip it in the fountain of youth. Then use a time-machine to meet Einstein and read his mind for some hints. </heavy irony>
  3. A

    Delay in design when we insert a MUX / DEMUX ??? Why ?

    All gates added in any path will add delay. Whether the delay added is acceptable or not depends on the specification and requirements of your design. If the design functionality need a multiplexer then you have to have it anyway.
  4. A

    [Help]Verilog Problem?

    If you had a later VCS version, using SystemVerilog mode when you compile, would allow your code.
  5. A

    Synthesis Warning:same net is connected to more than one pin

    Re: Synthesis Warning:same net is connected to more than one It may lead to assign statements in your final netlist which some back-end tools will not accept. This post: shows how to fix that problem. You can also get ruid of this by flattening/ungrouping the design
  6. A

    How to write code in Verilog for skipping two clock cycles at a time?

    Re: verilog doubt Every two clock cycles the output goes high for this verilog: assign z = 1'b1; Since you never specified when it needs to go low... Seriously, though. Your English is not clear on what you want, but I guess that you either want this: always @(posedge clk or negedge nrst)...
  7. A

    Verilog to VHDL converter ?

    If you dont mind the VHDL being a netlist, a synthesis tool will do the job. But any decent commercial simulator will do both languages
  8. A

    ICT coverage: W,RNQUIE: Simulation is complete?

    *w,rnquie It sounds like you dont have any testbench. If you try to run a simulation on just RTL you will get thsi behaviour, as there is no initial block providing stimulus for a clock, reste, etc.
  9. A

    How to know that a design has been verified completely?

    Re: verification coverage All programs, includign HDL designs, have at least one redundant line and one bug. therefore by repeatedly application of this theory, you can reduce any design to one line of code which doesn't work. :D
  10. A

    defining a port list of a decoder program in verilog

    There is not a "Cadence" tool: Cadence is a vendor. Cadence make lots of different tools: which one are you trying to use? What is the command you type to start it? I suspect that you may mean that you have created a verilog view in Design Framework 2 and the tool is reporting that it doesn't...
  11. A

    What is metastability and how to take care of avoiding it ?

    Re: metastability Well, two flip-flops in series usually is sufficient for eliminating metastability problems. This is becuase, whatever the mean time before failure for any given clock frequencies and phase relationships, it can be squared by having two flip-flops in series. So, it the MTBF...
  12. A

    How important is inserting DFT in ASIC design?

    Re: How important is DFT? For such a small design the DFT required would depend on the exact design: can you give any more details?
  13. A

    What circuit can make 125MHz clock to 1.25Ghz clock?

    clock 125mhz You'll want a DLL or PLL to increase the clock speed but going down is much easier: a counter circuit to divide can do that job.
  14. A

    why EX-OR in block and cyclic codes

    Well, I use the "+" symbol in my RTL for addition and XOR in CRCs as they are functionally correct. I then feed the RTL to a synthesiser which is free to use functionally equivalent logic to implement the design in the best time/area tradeoff according to my constraints. If it uses XORs in a...
  15. A

    circular buffer(its urgent)

    A circular buffer is an area of memory that wraps around from its top to its bottom, like a circle: hence the name.
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