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defining a port list of a decoder program in verilog

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estradasphere

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hi,

can you please tell me how to define a port list in cadence? I've written a small verilog decoder program in cadence, but without any success, since the port list fails. thanks in advance.
 

estradasphere said:
hi,

can you please tell me how to define a port list in cadence? I've written a small verilog decoder program in cadence, but without any success, since the port list fails. thanks in advance.
Hi,
2 suggestions:

1. Read a good Verilog book - before you send your code to a compiler.
2. Post your code to get feedback

Aji
www.noveldv.com
 

the verilog code i wrote can be compiled by ISE without any problems. All I want to know is how to create a port list in cadence,
 

Hi,
You should define the port information in verilog code with input/output/inout only. You should post detail error info or your RTL code to get more answer.

BR,
iamchine
 

Could you detail your problem?
 

Hi estradasphere,

Please detail your information about your code and your tool.
 

There is not a "Cadence" tool: Cadence is a vendor. Cadence make lots of different tools: which one are you trying to use? What is the command you type to start it?

I suspect that you may mean that you have created a verilog view in Design Framework 2 and the tool is reporting that it doesn't match with the symbol view: is that right? Maybe you are not specifying the bit widths of the ports correctly.
 

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