What is metastability and how to take care of avoiding it ?

[iTdl]

metastability

Hi I am new to this field and want to know what is metastability and how to take care of avoiding metastability while actual implementation? I am learning vhdl.

 

[sp]

Re: metastability

read any digital design/logic book... all of them explain nicely on tht,,

but i would personally promote this 2 books...

Digital Design - Principles and Practices 3rd Edition, John F. Wakerly; Prentice Hall

Digital Integrated Circuits - Design Perspective 2nd Edition, Jan M. Rabaey; Prentice Hall

2nd book is harder to understand.... and it cover IC/CMOS design as well..

regards,
sp

 

[amaccormack]

Re: metastability

Well, two flip-flops in series usually is sufficient for eliminating metastability problems.

This is becuase, whatever the mean time before failure for any given clock frequencies and phase relationships, it can be squared by having two flip-flops in series. So, it the MTBF was 1000s, it becomes 1000000s, which is longer than the uptime of an average chip anyway.

 

[dBUGGER]

metastability

Hi,
Digital design by john F. wakerley is really nice. Also you cna refer to cummings papers on asynchronous resets. That will also give you lots of ideas about the metastability issues. The important factor is MTBF, and as pointed two series FF's will give you sufficiently high MTBF.

Best Regards,

 

[semiconductorman]

Re: metastability

In digital logic all ur circuits should be either be in logic 1 or logic 0 . lets consider that 3.3v represents logic 1 and 0v represents logic 0 . so the circuit should be in one of the 2 voltage levels. Meta stablity is a condition where the voltage level is inbetween these 2 voltge levels . This does not represent a logic 0 or logic 1 and drives ur digital circuit crazy.
How is this caused
1. Using asynchronus resets -> consider the condition where reset is released exactly at the positive edge of ur clock . Should the Flipflop stay in reset state or capture what is in the data-in pin , usally what happens is that it goes to metastablilty.
2. When transfering data from one clock domain to another clock domain -> what if the data -in pin changed exactly at the positive edge of ur clock, again metastabilty !

Care u should take to avoid metastablilty 1. Use synchronus resets ( or atleast sychronize the reset release mechanism)
2. When transfering data across different clock domain use synchornizing flops

 

[bibo1978]

Re: metastability

in general metastability is an un avoidable behavior of circuit that may cause malfunction or failure when, this hazard can actually happen with any asynchronous signals passes to clocked circuit "this means that the signal can come from another uncorrelated clock clocked circuit", From a specification point of view, synchronous elements such as flip flops specify a Setup time and a Hold time. By its nature an asynchronous input cannot be reliably expected to meet this specification, and so it will have transitions that fall within the timing window that is bounded by these two specifications. When this occurs, the result can be one of three scenarios:
The state of the signal prior to the transition is used, the state of the signal after the transition is used or the flip flop goes metastable.
The third possibility is what matters here because in the two other situation the element will stay in it state or go to another state which is irrelevant to an asynchronous signal behavior.
So actaully asynchronous signal transition may violates the steup and hold time of the flipflop, however metastability actually occurs within a tiny timing window when the input doesnot violate the setup and hold timing specifications only but also when the flipflop accepts the new input, this causes an unstable equilibrium state under this symmertrically balanced transitory state is called the metastability. In fact the device may stop acting like a digital one and may act as an analog device, this also may cause a propagation of this situation to other cascaded elements in the circuit "you got a series of amplifiers for example", this may cause circuit failure or malfunction "not often to happen with CMOS". It is important to note that this behavior is described by what is called the Buriden principal which states that "A discrete decision based upon an input having a continuous range of values cannot be made within a bounded length of time", so actually the main problem lies due to the continuity of signal in time domain, the signal can lie between one and zero, and any continues signal needs an undertermined time to make right decision, it is funny to state that this principal holds in all physics, "including our daily descisoins". It is also impossible to determine how long such a state persists, so actually the metastability is described statistically, it is measured by the mean time between failure parameter (MTBF) which is inversely proportional to the product of the two frequencies involved, the clock frequency and the average frequency of the asynchronous data changes, provided that these two frequencies are independent and have no correlation.
To decrease the metastability hazard the most common technique is the metastability filter it might be a one or more FF, most commonly in nowadays designs is 2 cascaded FF, a metastability filter only decreases the metasatbility propability because it add a slack in its way.

that's all folks

 

[maksya]

Re: metastability

You can find some brief information about metastability here

h**p://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf

 

[barkha]

Re: metastability

some more link -
1. http://www.interfacebus.com/Design_MetaStable.html
2. klabs.org/richcontent/General_Application_Notes/ mestablestates/xilinx_metastable_considerations.pdf
3. www.cse.wustl.edu/~fred/ CLASSES/463FA03/Metastability.pdf

 

[rakeshnunna]

Re: metastability

Hi,

Even if set-up and hold times are not met, metastability may occur.So we have to make sure that we dont violate set-up and hold times.

regards

 

[anilkumarv]

Re: metastability

You can refer to the following doc for metastability.