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How to write code in Verilog for skipping two clock cycles at a time?

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naveen reddy

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How do i write code in verilog skipping two clock cycles at a time

(i.e) for every two clock cycles the output should go high
pls specify weather there is any condition to get this
 

verilog doubt

you can divide you clock by 2. and then use this clock to operate the ckt.
 

    V

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Re: verilog doubt

Every two clock cycles the output goes high for this verilog:

assign z = 1'b1;

Since you never specified when it needs to go low...

Seriously, though. Your English is not clear on what you want, but I guess that you either want this:

always @(posedge clk or negedge nrst)
if (~nrst) z <= 1'b0;
else z <= ~z;

which goes high every 2nd cycle

or this:

reg [1:0] c;
assign z=c[1];
always @(posedge clk or negedge nrst)
if (~nrst) c <= 2'b00;
else if (c==0) c <= 2'b10;
else c <= c - 2'b01;

which is low for 2 cycles then high in the 3rd cycle
 

Re: verilog doubt

This is what you are looking for.............
Hope this helps!
Code:
module div3 (clk, reset_n, out);
   input clk, reset_n;
   output      out;
   reg [2:0]   count;
   assign      out = count[1];
   
   always @(posedge clk or negedge reset_n)
     if (!reset_n)
       count <= 0;
     else
       if (count == 2'b10)
         count <= 0;
       else
         count <= count + 1;
endmodule // div3
 

Re: verilog doubt

you want to generate a signal whivh goes high for every 2 clock cycles.
i think this code will gives you that.

module ex(clk,reset,out);
input clk,reset;
output clk;

reg flag;

assign out = flag;

always @(posedge clk or negedge reset)
begin
if(!reset)
flag <= 0;
else
flag <= ~flag;
end

endmodule
 

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