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1. If the LDO and digital part in same chip, that's probably OK.
2. If discrete capless LDO to support other digital chip under design, you can do something to optimize, that is to spread your load current as evenly as possible in whole clock cycle, and put some inchip decoupling capacitors.
If you can dump verilog netlist from your schematic, you can go formal verification.
If you only have CDL (why not spice?), you need to make script program to convert CDL to verilog format, but in the converted verilog netlist, all ports have to be set as inout.
In general, the setup/hold time is positive. But, to help the design, we often design negative hold time for flip/flop, memory and so on, then designer only has to fix setup time violation.
In your SDF, there ofter are negatve timing.
Let me has an example, when the input signal of one buffer...
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