How to derive 5.2MHz clock from 25MHz clk in digital domain?

[chaitu2k]

clock generation

how di i derive 5.2MHz clock from 25 MHz clock in digital domain...i tried using counters but it does not give me the decimal part....

 

[dynoboy]

Re: clock generation

Hi dude,
this is a real challenging situation ...lets wait and see how many members can respond...
What I feel this is really a complicated secne is Digital Domain but you could go ahead and try PLL's or some such circuits....PLL you can change the ref voltage or some thing like that...

YET I'll try to figure this out soon i have already spread the word around, if i get some more info i will definately come back...

bye

 

[radiohead]

Re: clock generation

yes, 50MHz/125*13=5.2MHz. You have integrated PLL's on many common FPGA's. For ASIC design: you'll have to design them yourself! (should not be too difficult with respect to the frequency range).

But take care of clock phase alignment!

 

[albertyin]

clock generation

PLL can solve it.
But any easy way?

 

[metal]

Re: clock generation

Hello

You might use the frequency divider SN74LS292.

but unfortunately, you won't have a factor of 10, so you have to play around.

I have the datasheets from here :

https://focus.ti.com/docs/prod/folders/print/sn74ls292.html

Regards

 

[soccer]

clock generation

pll can solve it . if you want to use digital circuit to implement it, you can try to use FSM to generate multiple clocks.

 

[kkoko]

Re: clock generation

You can make a such oscillator with simple invertor and quarz.

 

[Teddy]

Re: clock generation

In case you use pll you just need prescaler as div by 26 and feedback divider of 125. That would giv it to you with precision of 6.5ppm