Capless LDO design can be implemented for digital current loading?

[suria3]

Hi Guys,

I need a help from the design expertise in the group. I like to get feedback if the "Capless LDO"
design can sustain/support for output digital circuit current loading, say 200-300mA peak current which is switching at 10MHz and above.

I have checked a number of journals that had implemented capless LDO design, but the measured
load transient is 150mA the most at 100pF caps which the output transient variations are not so good as well. So, I'm kind of puzzled if this is doable for the digital current loading for such a huge current spike and the requirement is to have output load voltage variation of less than 200mVpp without the using of Offchip large capacitor.....

Looking forward.

Thanks
Suria

 

[dick_freebird]

Capless LDOs can't respond instantaneously. They may
be better than older regulators but still their load step
advertised performance is predicated on a certain max
dI/dt which is probably quite leisurely compared to (say)
a FPGA going from idle to full-thrash in one clock cycle.

You need to look really carefully at the specsmanship
in play. You probably need to develop a worst case
load step (dI and dt) based on what you know about
the powered load, in order to assess suitability of any
LDO*capacitors combo, including purported "capless"
types.

 

[albertyin]

1. If the LDO and digital part in same chip, that's probably OK.
2. If discrete capless LDO to support other digital chip under design, you can do something to optimize, that is to spread your load current as evenly as possible in whole clock cycle, and put some inchip decoupling capacitors.