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Recent content by abaz

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    PSPICE transformer - floating nodes and grounds

    Sorry for the late reply and more so for possibly being mistaken... A long, long time ago (ie. Iv'e forgotten a lot) I struggled with transformer simulation in spice and started looking around for spice transformer models. The majority of the examples I found hardly ever used coupled inductors...
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    PSPICE transformer - floating nodes and grounds

    I think you'll find very few spice transformers that are modelled on coupling inductors, ideal or otherwise
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    PSPICE transformer - floating nodes and grounds

    Are you able to get it to generate a spice netlist that we can look at?
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    delay analog signal (continuous )

    I know very little about delay lines, so I'll pose this as a question. Is this really delaying the signal or are we just phase shifting the current and then using the current to develop a voltage accross a resistor? Is this method commonly used to delay signals? I have seen delay mechanisms for...
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    Generating energy and releasing energy through motor

    Makes you wonder, if you left out all the electrics and just put some lead in it would the momentum get it further up the hill than the motor... A study in the conservation of energy?
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    Generating energy and releasing energy through motor

    hmm... You haven't described the physics behind it but I beleive if you hooked a cap directly to the motor, assuming the motor will produce a dc voltage that is within the cap's specs, it may very well not have enough wieght to roll down the hill as a discharged cap will be an essential short...
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    [SOLVED] Can a PIC be programmed over the SPI bus ?

    If nobody posts more detailed help "PIC SPI Bootloader" would be the keywords to search.
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    Manufacturability of padless vias

    Thank you marce, its only through this recent search that I have come accross these design classes
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    Manufacturability of padless vias

    Thank you FvM I was thinking along the same lines. Stipulating a pad size the same as the finished drill size wouldn't be enough. You would have to take into account the finished wall size. Then there's dill placement tolorances, drill wable (Hole shadow?) etc, etc... which pretty much equates...
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    Manufacturability of padless vias

    I hate researching these things as it always raises more concerns. I have managed to find out more about vias, or plated through holes but haven't been able to find out the process or more importantly the order in which they carry them out. Given that they use electroplating to create the via...
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    Manufacturability of padless vias

    Thank you for your input FvM, not knowing the process what you say now concerns me a little. Are there any good sources of info on how PCB's are manufactured? If there's a risk I'd like to understand it little before taking it. I'll start searching now...
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    Manufacturability of padless vias

    Just got a reply back from the board house (PCB CART) The two pics I attached are the ones in the above post So, while not quite blind or burried, certainly more room on layers where we don't have to connect to... sweet!
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    Manufacturability of padless vias

    Thanks for the reply. Yes I will contact the board house but I just wanted to know if this was do-able with standard manufacturing techniques for future reference. Here's a graphical representation of what I mean The first pic shows the via with pads on all layers (for some reason its not...
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    Manufacturability of padless vias

    Taking into account my clearance constraints and polygon pours for power supply nets on a BGA device, I find that I'm not getting much connection metal between the vias that are not power supply ones. If I have full stack vias going through a multi layer board and decide to remove via pads on...
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    DC Link capacitor/filter for single phase inverter

    I would of thought the caps are to reduce ripple. It would be pointless to synthesize AC with PWM if the pulse levels werent at consisten amplitude

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