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Recent content by aarthy_maya

  1. aarthy_maya

    LVS Error with Mentor Calibre in hierarchy mode only, but LVS clean in Flat mode

    hi everyone, I have done a small circuit block, by utilizing power gating. So my top module have always ON module that tracks everything, and selectively powered modules. The layout is clean at all basic levels (both hierarchical and flat mode, with no extraction violations/warnings...
  2. aarthy_maya

    Functional Verification of using Multiple Testbench in System Verilog

    Hi ThisIsNotSam, Thank you for your response. It does work. I overlooked the problem. I got confused when, the initial stage (elab) take a while before kicking in the simulation. Initially I didn't wait for longer on my second test, since the first test took hours to complete. But...
  3. aarthy_maya

    Functional Verification of using Multiple Testbench in System Verilog

    Hi all, I am trying to do function verification using System Verilog. I have DUT developed in Verilog. The DUT is very complex. I would like to run multiple test on this DUT, from batch mode. The compilation and elaboration of the DUT takes long time in the whole simulation process. So I am...
  4. aarthy_maya

    Running Monte Carlo on VerilogA Variable with Synopsys Custom Designer

    Hi all, I am trying to run monte carlo analysis on a variable, from veriloga model. I had initially done the implementation with cadence-spectre flow. below is the example of how it is achieved in cadence-spectre. I put it here, so i can explain clearly what I want. 1. included the...
  5. aarthy_maya

    gm/Id in Cadence for multiple L values

    Re: hello sir you have plotted id/w vs gm/id ,can you please tell me how did you plot Hi, I believe you can use calculator function of ADE in case if you don't want for multiple L. Swept Vgs, W, and run a dc-analysis, Write Calculator function for id/w and gm/id separately. In VIVA you can...
  6. aarthy_maya

    Simulating Custom Verilog Modules with Cadence AMS simulato

    Simulating Custom Verilog Modules with Cadence AMS simulator Hi Everyone, Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock. I have imported all the 3 modules separately and created a schematic view and config view. I have also declared...
  7. aarthy_maya

    Assigning Value for Logic 1 in Verilog testbench

    Hi, I am newbie to Verilog. I am trying to write a test-bench for my custom design circuits using Verilog. The Simulation is done in Cadence ADE using AMS simulator. The problem is, the PDK uses two different voltages (1.8/3.3V), so when I run the simulation, the Value of logic 1 is at 1.8V. I...
  8. aarthy_maya

    Exporting data from Cadence ADE or from VIVA

    Thanks Sarge!
  9. aarthy_maya

    Exporting data from Cadence ADE or from VIVA

    I am aware of it, but that will export my entire time scale, as i mentioned I am only interested in a particular time, say if I run 0-200ns trans analysis, I want to export the data value only at for ex: 100ns. I don't want data from the whole time scale(x axis). Thanks! Aarthy
  10. aarthy_maya

    Exporting data from Cadence ADE or from VIVA

    Hi, I am looking for the dumping the variable from cadence ADE/VIVA for a particular instant of time. I am running a trans simulation, I need to export the data for a particular instant of time into a txt/xls/csv file so I can use it to plot trend curves. I was using markers and noting down...
  11. aarthy_maya

    Setting Initial Condition on Internal nodes in Verilog A

    I have to write a behavioral model for device. There is, say for example 3 external node(IO) and one Internal node. When i run the model with Spectre, there is a convergence error as the tool was not able to compute the DC operating point. So I am trying to set initial condition on the internal...
  12. aarthy_maya

    Relation between slew rate and minimum closed loop gain

    Hi FvM, Thanks for the reply! I understand it now.
  13. aarthy_maya

    Relation between slew rate and minimum closed loop gain

    Hi FvM, the reference "http://books.google.com.sg/books?id=V-N4jbgbo9sC&pg=PA84&lpg=PA84&dq=feedforward+compensation+in+operational+amplifier&source=bl&ots=lQTpe6aLmd&sig=JHHu8IhnhEmzpgxhVArzgcmcXD0&hl=en&sa=X&ei=C-qET-_6KozPrQfOtrSxBg&ved=0CDMQ6AEwAg#v=onepage&q&f=false" on page 4 (i have...
  14. aarthy_maya

    Relation between slew rate and minimum closed loop gain

    Hi all, I am looking for the relation between the minimum closed loop gain and slew rate?? can someone help?? Thanks! Aarthy
  15. aarthy_maya

    Bandwidth for Voltage mode and current mode technique

    Thanks LvW... the link quite useful for understanding
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