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Functional Verification of using Multiple Testbench in System Verilog

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aarthy_maya

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Hi all,

I am trying to do function verification using System Verilog. I have DUT developed in Verilog. The DUT is very complex.
I would like to run multiple test on this DUT, from batch mode. The compilation and elaboration of the DUT takes long time in the whole simulation process.
So I am wondering is there a way I can compile, elaborate the DUT alone (leaving the IO, top level test-bench and stimulus generator) and store it a place, and use this elaborated library with say test0.sv, test1.sv and so on in the later stage. As there is literally no change in DUT.

Could some one help me on this. Whether what I'am considering is sane way to do the verification. ?

On additional note, I am using Cadence Incisive Simulator. I tried to learn the snapshot concept. Since I am new to this functional verification, I don't understand the functionality of snapshot. Could someone also explain whether snapshot concept is meant for this method(multiple test bench on Singe DUT) of functional verification?

Thank you in advance.

Regards,
Aarthy
 

cadence simulators do this automatically, just keep running in the same folder. the DUT will not be re-elaborated. you don't need snapshots.
 
Hi ThisIsNotSam,

Thank you for your response.

It does work. I overlooked the problem. I got confused when, the initial stage (elab) take a while before kicking in the simulation. Initially I didn't wait for longer on my second test, since the first test took hours to complete. But, now after your response, I Let it run and It ended in less than an hour. Now I understand, the initial time might be due to verification, to make sure there is no change in source code(DUT)

Regards,
Aarthy
 

Hi ThisIsNotSam,

Thank you for your response.

It does work. I overlooked the problem. I got confused when, the initial stage (elab) take a while before kicking in the simulation. Initially I didn't wait for longer on my second test, since the first test took hours to complete. But, now after your response, I Let it run and It ended in less than an hour. Now I understand, the initial time might be due to verification, to make sure there is no change in source code(DUT)

Regards,
Aarthy

the comparison is usually pretty fast, it is based on timestamps. maybe you are seeing big elab times because the testbench is actually big? or it might be the case that no new elaboration takes place for the DUT, but the previous elaborated version still takes a big amount of time to load.
 

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