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Threads 1 to 30 of 19047

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 03:22
    • Replies: 2
    • Views: 6,232
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 13,655
    21st March 2007, 21:21 Go to last post
    • Replies: 3
    • Views: 62
    Today, 13:12 Go to last post
  1. Binning + Pipeline, How to do it, please?

    Started by flote21, 11th October 2014 16:38
    • Replies: 17
    • Views: 723
    Today, 08:44 Go to last post
    • Replies: 5
    • Views: 157
    Today, 06:36 Go to last post
    • Replies: 0
    • Views: 67
    Today, 03:58 Go to last post
    • Replies: 7
    • Views: 109
    Yesterday, 18:49 Go to last post
  2. doubt about static timing analysis

    Started by kommu4946, 22nd May 2014 05:23
    2 Pages
    1 2
    • Replies: 26
    • Views: 899
    Yesterday, 16:49 Go to last post
    • Replies: 1
    • Views: 244
    Yesterday, 16:06 Go to last post
    • Replies: 2
    • Views: 120
    Yesterday, 15:28 Go to last post
  3. Generating a pulse of 100ns

    Started by mehanathan, 17th October 2014 04:28
    • Replies: 8
    • Views: 356
    Yesterday, 13:01 Go to last post
    • Replies: 1
    • Views: 71
    Yesterday, 10:33 Go to last post
  4. Doubt in Modelsim, simulation taking more time, I am doing correctly?

    Started by abu9022, 19th October 2014 17:52
    2 Pages
    1 2
    • Replies: 23
    • Views: 393
    20th October 2014, 18:06 Go to last post
  5. sdf file Error: Failed to find instance

    Started by abu9022, 20th October 2014 06:04
    • Replies: 3
    • Views: 143
    20th October 2014, 17:54 Go to last post
    • Replies: 4
    • Views: 197
    20th October 2014, 05:49 Go to last post
  6. xilinx timing analysis report

    Started by arishsu, 17th October 2014 03:52
    • Replies: 9
    • Views: 428
    20th October 2014, 05:35 Go to last post
  7. Wireless Video starter Kit

    Started by mkrtich.nazaryan, 20th October 2014 02:31
    • Replies: 0
    • Views: 89
    20th October 2014, 02:31 Go to last post
  8. decoder verilog code

    Started by vead, 17th October 2014 14:41
    • Replies: 9
    • Views: 411
    19th October 2014, 18:52 Go to last post
  9. [SOLVED] Verror 3033 the design unit was not found

    Started by abu9022, 18th October 2014 22:14
    • Replies: 4
    • Views: 278
    19th October 2014, 17:25 Go to last post
    • Replies: 3
    • Views: 154
    FvM
    19th October 2014, 17:00 Go to last post
  10. FPGA Development tool xilinx or Altera

    Started by ep.hobbyiest, 17th October 2014 18:46
    • Replies: 7
    • Views: 410
    19th October 2014, 15:46 Go to last post
  11. sin wave multiplication using IP Cores -

    Started by Christian Chetcuti, 19th October 2014 11:25
    • Replies: 2
    • Views: 113
    19th October 2014, 12:20 Go to last post
  12. do functions synthesize to combinational logic?

    Started by shainky, 2nd October 2014 18:13
    • Replies: 8
    • Views: 831
    FvM
    18th October 2014, 16:38 Go to last post
  13. Quick Verilog question

    Started by vlad928, 18th October 2014 05:29
    • Replies: 2
    • Views: 239
    18th October 2014, 10:02 Go to last post
  14. Vhdl code for 4-bit parallel access shift registers

    Started by krisdan, 17th October 2014 11:21
    • Replies: 2
    • Views: 116
    17th October 2014, 13:20 Go to last post
    • Replies: 1
    • Views: 135
    17th October 2014, 04:06 Go to last post
    • Replies: 2
    • Views: 135
    16th October 2014, 18:25 Go to last post
  15. 01010 Sequence detector

    Started by Ashishmko, 15th October 2014 18:31
    • Replies: 5
    • Views: 361
    16th October 2014, 16:44 Go to last post
  16. Need help on pipelining in square root using verilog

    Started by dipin, 15th October 2014 12:44
    • Replies: 11
    • Views: 431
    16th October 2014, 16:26 Go to last post
  17. Motion estimation video processing

    Started by invlsi, 16th October 2014 07:49
    • Replies: 1
    • Views: 160
    16th October 2014, 11:50 Go to last post
  18. To display a square on monitor ( Verilog vga Basys 2 board )

    Started by sukanya28, 13th October 2014 10:56
    2 Pages
    1 2
    • Replies: 25
    • Views: 840
    16th October 2014, 07:20 Go to last post
  19. read an image in sram

    Started by innovaga, 16th October 2014 06:10
    • Replies: 1
    • Views: 159
    16th October 2014, 06:47 Go to last post

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