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Threads 1 to 30 of 21957

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 22,305
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 28,094
    21st March 2007, 21:21 Go to last post
  1. MachXO2 DDR and PCLK routing issue

    Started by juanMco, Today 17:32
    • Replies: 1
    • Views: 133
    Today, 22:40 Go to last post
  2. FPGA interface with 100Mbps Ethernet

    Started by fouwad, 17th November 2017 07:10
    • Replies: 3
    • Views: 827
    Today, 14:26 Go to last post
  3. Help tracking down very long synthesis time

    Started by whaleeee, 13th November 2017 19:51
    • Replies: 13
    • Views: 1,186
    Today, 08:48 Go to last post
  4. [SOLVED] concurrent vhdl code generating latches

    Started by rafimiet, Yesterday 10:10
    • Replies: 4
    • Views: 571
    Yesterday, 11:43 Go to last post
  5. [moved] ZedBoard HDMI input without FMC card

    Started by DilshanSampath, 17th November 2017 18:13
    • Replies: 2
    • Views: 430
    18th November 2017, 20:02 Go to last post
  6. Moving window integrator

    Started by Rani1234, 17th November 2017 12:43
    • Replies: 4
    • Views: 329
    17th November 2017, 18:38 Go to last post
  7. [SOLVED] Initializing Xilinx BRAM with image pixels

    Started by Taki_comp, 6th November 2017 20:52
    • Replies: 10
    • Views: 1,016
    17th November 2017, 14:38 Go to last post
  8. fir band pass filter using verilog

    Started by josephine1234, 17th November 2017 10:30
    • Replies: 6
    • Views: 298
    17th November 2017, 11:05 Go to last post
  9. Xilinx ISE - readmemh system task taking too much time

    Started by NikosTS, 14th November 2017 11:36
    • Replies: 1
    • Views: 270
    17th November 2017, 07:11 Go to last post
    • Replies: 1
    • Views: 423
    16th November 2017, 17:04 Go to last post
  10. vhdl coding techniques

    Started by manishpatkar, 13th November 2017 12:55
    • Replies: 16
    • Views: 928
    16th November 2017, 15:01 Go to last post
  11. Missing JESD parameters in Xilinx JESD204 IP Rx!!

    Started by samg, 15th November 2017 05:46
    • Replies: 2
    • Views: 344
    15th November 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 505
    14th November 2017, 23:20 Go to last post
    • Replies: 1
    • Views: 203
    14th November 2017, 18:17 Go to last post
  12. Sending data sequentially

    Started by beginner_EDA, 8th November 2017 12:42
    • Replies: 6
    • Views: 511
    14th November 2017, 13:24 Go to last post
    • Replies: 3
    • Views: 752
    13th November 2017, 21:38 Go to last post
    • Replies: 3
    • Views: 908
    13th November 2017, 12:00 Go to last post
  13. Configuring JESD parameters in Xilinx JESD204

    Started by samg, 13th November 2017 07:01
    • Replies: 0
    • Views: 346
    13th November 2017, 07:01 Go to last post
    • Replies: 1
    • Views: 779
    11th November 2017, 13:03 Go to last post
  14. MAX10 PLL External Clock Output

    Started by Yorki, 9th November 2017 14:35
    • Replies: 6
    • Views: 571
    11th November 2017, 11:39 Go to last post
  15. [SOLVED] Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    2 Pages
    1 2
    • Replies: 31
    • Views: 3,535
    10th November 2017, 17:33 Go to last post
  16. Moved: IGMP Packet generating software

    Started by beginner_EDA, 10th November 2017 16:10
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    •  
    • Replies: 12
    • Views: 1,322
    9th November 2017, 20:04 Go to last post
    • Replies: 1
    • Views: 321
    9th November 2017, 17:10 Go to last post
    • Replies: 3
    • Views: 509
    8th November 2017, 18:49 Go to last post
    • Replies: 2
    • Views: 315
    8th November 2017, 13:03 Go to last post
    • Replies: 14
    • Views: 1,689
    8th November 2017, 02:58 Go to last post
    • Replies: 3
    • Views: 401
    7th November 2017, 18:30 Go to last post
  17. LCD code for fpga virtex 6

    Started by moonshine8995, 6th November 2017 12:39
    • Replies: 3
    • Views: 611
    7th November 2017, 13:08 Go to last post
  18. Verilog basic coding/naming conventions

    Started by pigtwo, 4th November 2017 21:53
    • Replies: 7
    • Views: 795
    6th November 2017, 04:44 Go to last post