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Threads 1 to 30 of 19212

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 6,547
    2nd June 2013, 17:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 22:21
    • Replies: 0
    • Views: 13,886
    21st March 2007, 22:21 Go to last post
    • Replies: 3
    • Views: 99
    Today, 21:16 Go to last post
  1. fifo implementation using a counter

    Started by sandy3129, 16th November 2014 13:32
    2 Pages
    1 2
    • Replies: 34
    • Views: 1,596
    Today, 19:07 Go to last post
  2. system verilog input randamization problem

    Started by dipin, 26th November 2014 12:36
    • Replies: 5
    • Views: 692
    Today, 12:54 Go to last post
    • Replies: 6
    • Views: 508
    Today, 11:32 Go to last post
  3. How to increment a value in verilog?

    Started by keerthna, Today 09:45
    • Replies: 4
    • Views: 87
    Today, 10:49 Go to last post
    • Replies: 0
    • Views: 70
    Today, 10:47 Go to last post
    • Replies: 1
    • Views: 78
    Today, 09:05 Go to last post
  4. How to use D Latch in RTL

    Started by dhanya22, Yesterday 14:29
    • Replies: 5
    • Views: 158
    Today, 09:03 Go to last post
  5. Upsampling a signal from UART

    Started by Christian Chetcuti, Yesterday 20:40
    • Replies: 5
    • Views: 117
    Yesterday, 22:31 Go to last post
  6. CLOCK connected to non global clock pin

    Started by axcdd, Yesterday 13:09
    • Replies: 4
    • Views: 119
    Yesterday, 18:32 Go to last post
    • Replies: 3
    • Views: 98
    Yesterday, 18:02 Go to last post
    • Replies: 7
    • Views: 85
    Yesterday, 17:52 Go to last post
    • Replies: 2
    • Views: 107
    Yesterday, 17:46 Go to last post
  7. padding of zeros llogic in verilog

    Started by anusha vasanta, 26th November 2014 09:52
    • Replies: 15
    • Views: 428
    Yesterday, 17:40 Go to last post
  8. handshaking signals for uart

    Started by DEVI403, 24th November 2014 05:33
    • Replies: 2
    • Views: 246
    Yesterday, 17:23 Go to last post
  9. iimplementation to FPGA

    Started by rekhavp, 26th November 2014 16:55
    • Replies: 7
    • Views: 178
    Yesterday, 06:48 Go to last post
  10. What can cause synthesis-dependent intermittents?

    Started by Artlav, 25th November 2014 23:50
    • Replies: 5
    • Views: 401
    Yesterday, 00:31 Go to last post
  11. Is it just me? ...............

    Started by mrflibble, 26th November 2014 11:26
    • Replies: 9
    • Views: 407
    26th November 2014, 23:12 Go to last post
  12. Refactoring revisited

    Started by mrflibble, 26th November 2014 11:16
    • Replies: 6
    • Views: 286
    26th November 2014, 20:38 Go to last post
  13. function of Adder and MUX in the given

    Started by vishal_sonam, 26th November 2014 19:47
    • Replies: 2
    • Views: 144
    26th November 2014, 20:13 Go to last post
  14. I need to learn VHDL.

    Started by vishal_sonam, 26th November 2014 08:46
    • Replies: 6
    • Views: 311
    26th November 2014, 19:21 Go to last post
  15. Canny Edge Detector in XSG

    Started by nick123, 21st November 2014 10:53
    • Replies: 3
    • Views: 422
    26th November 2014, 18:58 Go to last post
  16. 16x4 memory using behavioral model

    Started by Ayyappa Gollu, 22nd November 2014 20:56
    • Replies: 3
    • Views: 376
    26th November 2014, 16:34 Go to last post
  17. any one famiar with PLDA EZDMA PCIe Core?

    Started by Port Map, 26th November 2014 14:24
    • Replies: 0
    • Views: 100
    26th November 2014, 14:24 Go to last post
  18. What is an “overlapped instruction execution”?

    Started by vishal_sonam, 26th November 2014 10:21
    • Replies: 1
    • Views: 177
    26th November 2014, 10:32 Go to last post
  19. differences between for...loop and for...generate

    Started by Binome, 25th November 2014 16:50
    • Replies: 6
    • Views: 366
    26th November 2014, 08:36 Go to last post
    • Replies: 0
    • Views: 145
    26th November 2014, 07:15 Go to last post
    • Replies: 3
    • Views: 313
    26th November 2014, 07:09 Go to last post
  20. [SOLVED] how to increment a counter for 5 cycles.

    Started by prashanthi999, 25th November 2014 16:29
    • Replies: 4
    • Views: 367
    26th November 2014, 04:26 Go to last post
  21. crc 32 ethernet-magic number

    Started by Nandini Ganig, 26th November 2014 02:55
    • Replies: 0
    • Views: 199
    26th November 2014, 02:55 Go to last post

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