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Threads 1 to 30 of 19287

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 6,742
    2nd June 2013, 17:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 22:21
    • Replies: 0
    • Views: 14,033
    21st March 2007, 22:21 Go to last post
  1. Xilinx Kintex STARTUPE2

    Started by barry, Today 16:57
    • Replies: 2
    • Views: 54
    Today, 20:24 Go to last post
  2. Sizing a VHDL input port

    Started by shaiko, 16th December 2014 12:17
    2 Pages
    1 2
    • Replies: 25
    • Views: 520
    Today, 20:15 Go to last post
    • Replies: 3
    • Views: 101
    Today, 17:58 Go to last post
  3. Synthesizing encrypted RTL using Xilinx ISE

    Started by fahum, Yesterday 16:34
    • Replies: 3
    • Views: 119
    Today, 13:28 Go to last post
  4. Rising edge of IN- what does it mean.

    Started by vishal_sonam, Yesterday 20:33
    • Replies: 3
    • Views: 116
    Today, 09:23 Go to last post
    • Replies: 1
    • Views: 60
    Today, 06:46 Go to last post
  5. Tools supporting verilog-2001

    Started by anusha vasanta, 15th December 2014 10:27
    • Replies: 6
    • Views: 296
    Yesterday, 22:35 Go to last post
  6. VHDL How to Design a Screen (Frame) Buffer

    Started by yttuncel, 16th December 2014 20:31
    • Replies: 3
    • Views: 231
    Yesterday, 19:58 Go to last post
  7. better ways to clock divisions

    Started by bharath9, Yesterday 06:03
    • Replies: 4
    • Views: 178
    Yesterday, 19:00 Go to last post
  8. 5V Stepper motor 28BYJ-48

    Started by Sweta25, Yesterday 11:22
    • Replies: 3
    • Views: 124
    FvM
    Yesterday, 14:57 Go to last post
  9. Xilinx LogiCore Block Problem

    Started by koshmar29, 15th December 2014 22:39
    • Replies: 7
    • Views: 272
    Yesterday, 06:39 Go to last post
    • Replies: 2
    • Views: 210
    Yesterday, 05:43 Go to last post
  10. 16-bit register scaling to drive MDACs

    Started by sawaak, 16th December 2014 08:06
    • Replies: 0
    • Views: 92
    16th December 2014, 08:06 Go to last post
  11. Using buffer and shifting in VHDL problem

    Started by ghattas.akkad, 15th December 2014 21:40
    • Replies: 2
    • Views: 123
    15th December 2014, 23:57 Go to last post
  12. VHDL for Real time applications

    Started by Y.SAI SARASWATHI, 15th December 2014 14:44
    • Replies: 1
    • Views: 154
    15th December 2014, 20:32 Go to last post
  13. [SOLVED] CPU: am designing a 4 bit CPU using VHDL on quartus 2 for altera .

    Started by axi3795, 14th December 2014 16:59
    • Replies: 3
    • Views: 235
    15th December 2014, 20:12 Go to last post
  14. spi slave code in vhdl

    Started by DEVI403, 12th December 2014 13:15
    • Replies: 2
    • Views: 122
    15th December 2014, 18:49 Go to last post
  15. sine table to Audio CODEC line out de2-70 vhdl

    Started by jackobian, 13th December 2014 04:51
    • Replies: 2
    • Views: 193
    15th December 2014, 18:45 Go to last post
  16. Concept of Negative setup time

    Started by VirtuosoDracula, 12th December 2014 09:11
    • Replies: 2
    • Views: 176
    15th December 2014, 12:45 Go to last post
    • Replies: 1
    • Views: 54
    15th December 2014, 12:35 Go to last post
  17. Polynomial Division on hardware

    Started by ghattas.akkad, 13th December 2014 19:15
    • Replies: 1
    • Views: 186
    15th December 2014, 11:36 Go to last post
    • Replies: 1
    • Views: 156
    12th December 2014, 18:01 Go to last post
  18. How to create a sine wave using lut in verilog?

    Started by keerthna, 9th December 2014 09:48
    • Replies: 10
    • Views: 377
    12th December 2014, 17:11 Go to last post
  19. regarding time-scale in verilog

    Started by anusha vasanta, 5th December 2014 05:33
    • Replies: 2
    • Views: 280
    12th December 2014, 14:13 Go to last post
  20. Source code -MESA - Horner Bezier

    Started by snehalkate, 11th December 2014 11:13
    • Replies: 1
    • Views: 143
    12th December 2014, 14:05 Go to last post
  21. Matlab hamming to vhdl 8-bit

    Started by OS_cilloscope, 12th December 2014 03:22
    • Replies: 1
    • Views: 175
    12th December 2014, 09:53 Go to last post
  22. Did I correctly implement this SR-Latch and D-Latch?

    Started by delta136, 10th December 2014 13:33
    • Replies: 9
    • Views: 305
    11th December 2014, 17:41 Go to last post
  23. How to extend 4-bit barrel shifter to 32-bit?

    Started by delta136, 10th December 2014 22:28
    • Replies: 5
    • Views: 166
    11th December 2014, 01:57 Go to last post
  24. Serial to Parallel Converter VHDL codes

    Started by Sweta25, 10th December 2014 17:50
    • Replies: 2
    • Views: 152
    10th December 2014, 20:11 Go to last post
  25. Offset meaning in programming language

    Started by shan14, 10th December 2014 12:02
    • Replies: 2
    • Views: 145
    10th December 2014, 16:07 Go to last post

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