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Threads 1 to 30 of 21047

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 03:22
    • Replies: 2
    • Views: 14,089
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 21,539
    21st March 2007, 21:21 Go to last post
  1. why can't I write in the memory?

    Started by hamidkavianathar, 27th September 2016 06:11
    • Replies: 10
    • Views: 263
    Today, 08:33 Go to last post
  2. Help me in understanding Verilog constructs

    Started by Ganesan_R, 27th September 2016 00:58
    • Replies: 9
    • Views: 237
    Today, 06:26 Go to last post
  3. communication between Matlab and FPGA virtex 5

    Started by Taki_comp, 20th September 2016 12:19
    • Replies: 4
    • Views: 249
    Yesterday, 12:56 Go to last post
    • Replies: 0
    • Views: 87
    Yesterday, 11:48 Go to last post
    • Replies: 9
    • Views: 245
    26th September 2016, 22:19 Go to last post
  4. Is this an efficient Verilog code

    Started by David83, 24th September 2016 04:33
    • Replies: 19
    • Views: 295
    26th September 2016, 19:52 Go to last post
  5. Verilog code Error in ISIM

    Started by Rustum, 25th September 2016 10:25
    • Replies: 2
    • Views: 162
    26th September 2016, 19:46 Go to last post
  6. Constraining a design with "pass through" signals

    Started by shaiko, 24th September 2016 12:03
    • Replies: 17
    • Views: 255
    26th September 2016, 19:33 Go to last post
  7. FPGA-to-HPS SDRAM Bridge in Bare-metal

    Started by Mechatronics_eng, 26th September 2016 13:04
    • Replies: 0
    • Views: 115
    26th September 2016, 13:04 Go to last post
  8. Specifying input and output delays for UART

    Started by biju4u90, 26th September 2016 06:03
    • Replies: 1
    • Views: 123
    26th September 2016, 08:47 Go to last post
  9. [moved] Vhdl Code For Ladner Fischer Adder

    Started by Kumar_11, 24th September 2016 13:29
    • Replies: 0
    • Views: 151
    24th September 2016, 13:29 Go to last post
  10. Synthesis tool - meeting hold time constrains

    Started by shaiko, 23rd September 2016 20:28
    • Replies: 3
    • Views: 169
    24th September 2016, 08:35 Go to last post
  11. FPGA: waveform monitor

    Started by beginner_EDA, 19th September 2016 08:43
    • Replies: 6
    • Views: 240
    23rd September 2016, 13:44 Go to last post
    • Replies: 3
    • Views: 175
    FvM
    23rd September 2016, 07:23 Go to last post
  12. Zynq UART Baud Rate Limit and IP Cores

    Started by bieaisar7, 21st September 2016 09:55
    • Replies: 7
    • Views: 174
    FvM
    22nd September 2016, 17:24 Go to last post
  13. How to export and view waveform after UVM ?

    Started by slutarius, 21st September 2016 09:38
    • Replies: 6
    • Views: 187
    22nd September 2016, 14:40 Go to last post
  14. Logic block updating Nios

    Started by nsgil85, 22nd September 2016 09:50
    • Replies: 0
    • Views: 142
    22nd September 2016, 09:50 Go to last post
  15. fpga design flows - help needed

    Started by J_M_B, 22nd September 2016 08:02
    • Replies: 1
    • Views: 148
    22nd September 2016, 08:13 Go to last post
  16. Project based on altera

    Started by bellu, 20th September 2016 11:00
    • Replies: 3
    • Views: 162
    22nd September 2016, 08:10 Go to last post
    • Replies: 0
    • Views: 120
    22nd September 2016, 05:47 Go to last post
  17. vhdl for loop indicese

    Started by Binome, 21st September 2016 11:02
    • Replies: 5
    • Views: 163
    21st September 2016, 16:36 Go to last post
    • Replies: 1
    • Views: 146
    21st September 2016, 16:09 Go to last post
  18. High utilization and timing vioalations

    Started by UltraGreen, 20th September 2016 05:18
    • Replies: 13
    • Views: 229
    21st September 2016, 16:00 Go to last post
  19. Protected Registered PAL REV ENG

    Started by apprenticemart2, 20th September 2016 14:34
    • Replies: 0
    • Views: 171
    20th September 2016, 14:34 Go to last post
  20. FPGA learning Curve!

    Started by J_M_B, 19th September 2016 07:58
    • Replies: 2
    • Views: 240
    20th September 2016, 09:11 Go to last post
  21. VHDL code for RC4 algorithm for encryption

    Started by Sunayana Chakradhar, 19th September 2016 08:34
    • Replies: 4
    • Views: 188
    20th September 2016, 05:39 Go to last post
  22. [SOLVED] String signal on testbench

    Started by nsgil85, 18th September 2016 12:22
    • Replies: 6
    • Views: 210
    19th September 2016, 13:34 Go to last post
  23. Modulus/reminder operation in FPGA

    Started by mjuneja, 16th September 2016 11:57
    • Replies: 4
    • Views: 231
    18th September 2016, 18:13 Go to last post
  24. Best Books To Learn Verilog HDL

    Started by David83, 16th September 2016 17:16
    • Replies: 5
    • Views: 265
    17th September 2016, 09:58 Go to last post
  25. Having an FPGA board?

    Started by David83, 15th September 2016 04:41
    • Replies: 13
    • Views: 279
    16th September 2016, 16:58 Go to last post

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