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Threads 1 to 30 of 18948

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 03:22
    • Replies: 2
    • Views: 5,970
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 13,481
    21st March 2007, 21:21 Go to last post
  1. leaving a VHDL port open

    Started by shaiko, Today 10:53
    • Replies: 0
    • Views: 4
    Today, 10:53 Go to last post
  2. Spartan 3E LCD verilog code problem

    Started by arishsu, 11th September 2014 06:07
    • Replies: 1
    • Views: 115
    Today, 06:16 Go to last post
  3. FPGA, Power Electronics, SMPS, Control

    Started by Varun Chitransh, 18th September 2014 19:11
    • Replies: 3
    • Views: 267
    Today, 02:28 Go to last post
    • Replies: 4
    • Views: 82
    Yesterday, 21:41 Go to last post
  4. [SOLVED] how can i read from memory

    Started by Mina Magdy, Yesterday 20:34
    • Replies: 1
    • Views: 64
    Yesterday, 20:51 Go to last post
  5. dumping the code on FPGA kit ...

    Started by gnseeta.btech, 19th September 2014 05:41
    • Replies: 15
    • Views: 336
    Yesterday, 20:14 Go to last post
  6. How to give power to SIM908 Antenna

    Started by Amalinda, 10th June 2013 02:15
    • Replies: 6
    • Views: 516
    FvM
    Yesterday, 18:53 Go to last post
  7. Any good free software to draw logic signals

    Started by Sink0, 20th May 2011 20:01
    • Replies: 18
    • Views: 3,594
    Yesterday, 17:08 Go to last post
  8. vhdl signal definition

    Started by shaiko, Yesterday 02:10
    • Replies: 3
    • Views: 137
    K-J
    Yesterday, 13:27 Go to last post
  9. manual routing vs autorouting using ISE

    Started by verylsi, 19th September 2014 12:40
    • Replies: 4
    • Views: 111
    19th September 2014, 15:54 Go to last post
  10. Online arithmetic with radix 2 addition

    Started by ghattas.akkad, 17th September 2014 14:38
    • Replies: 2
    • Views: 297
    18th September 2014, 18:36 Go to last post
  11. Calculate Sum of (z[n])^2 in VHDL!

    Started by NorthZ, 18th September 2014 13:53
    • Replies: 5
    • Views: 129
    18th September 2014, 16:27 Go to last post
  12. How to reduce usage of bonded IOBs

    Started by arishsu, 14th September 2014 12:16
    • Replies: 9
    • Views: 264
    18th September 2014, 16:19 Go to last post
  13. A few questions about Verilog

    Started by shaiko, 17th September 2014 07:36
    • Replies: 14
    • Views: 223
    FvM
    17th September 2014, 22:23 Go to last post
  14. component instantiation and synthesis

    Started by shikharmakkar, 16th September 2014 02:08
    • Replies: 8
    • Views: 228
    17th September 2014, 18:41 Go to last post
  15. square root of a number

    Started by dipin, 17th September 2014 10:22
    • Replies: 3
    • Views: 127
    FvM
    17th September 2014, 17:12 Go to last post
  16. VHDL Synthesis Code help ,required clarification.

    Started by Y.SAI SARASWATHI, 16th September 2014 15:17
    • Replies: 6
    • Views: 184
    K-J
    17th September 2014, 16:40 Go to last post
  17. cannot open macro file: system.do

    Started by mahound, 16th September 2014 18:05
    • Replies: 2
    • Views: 98
    17th September 2014, 16:28 Go to last post
  18. VHDL Program for a 4 bit full-adder

    Started by fm_com_28, 10th October 2006 21:33
    • Replies: 5
    • Views: 42,304
    17th September 2014, 09:24 Go to last post
  19. [SOLVED] Signed multiplier in Verilog. "signed" doesn't work

    Started by oak_tree, 15th September 2014 23:16
    • Replies: 6
    • Views: 231
    16th September 2014, 20:14 Go to last post
  20. 6 3phase motor speed inverter help

    Started by janosandi, 23rd July 2014 23:43
    • Replies: 7
    • Views: 311
    16th September 2014, 19:49 Go to last post
    • Replies: 1
    • Views: 93
    16th September 2014, 16:33 Go to last post
  21. [SOLVED] verilog: how to find max value in the bus

    Started by miskod, 16th September 2014 10:31
    • Replies: 1
    • Views: 105
    16th September 2014, 12:45 Go to last post
  22. [SOLVED] Suggestions for CISC and RISC cores for university use

    Started by dpaul, 12th September 2014 10:13
    • Replies: 2
    • Views: 144
    16th September 2014, 12:25 Go to last post
  23. [SOLVED] Matlab and Modelsim Cosimulation

    Started by sameh_yassin99, 31st October 2011 16:50
    • Replies: 7
    • Views: 2,421
    16th September 2014, 10:07 Go to last post
  24. [SOLVED] uniformly distributed random number [0,1]

    Started by rakeshk.r, 15th September 2014 17:11
    • Replies: 7
    • Views: 165
    16th September 2014, 09:26 Go to last post
  25. Simulating a design with Altera PLL in modelsim

    Started by shaiko, 15th September 2014 11:09
    • Replies: 9
    • Views: 146
    15th September 2014, 23:54 Go to last post
  26. can anyone help me build a 5x5 bit signed multiplier

    Started by aishak_97, 15th September 2014 16:46
    • Replies: 2
    • Views: 150
    15th September 2014, 23:48 Go to last post
  27. Trying to run Nios LED code ?

    Started by bianchi77, 15th September 2014 12:03
    • Replies: 2
    • Views: 101
    15th September 2014, 22:26 Go to last post
  28. verilog code for input output

    Started by vead, 15th September 2014 16:03
    • Replies: 1
    • Views: 85
    15th September 2014, 16:12 Go to last post

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