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Threads 1 to 30 of 19418

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 7,130
    2nd June 2013, 17:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 22:21
    • Replies: 0
    • Views: 14,342
    21st March 2007, 22:21 Go to last post
  1. [SOLVED] Verilog Loop operation with registers.

    Started by ismailov-e, 26th January 2015 11:59
    • Replies: 13
    • Views: 378
    Yesterday, 20:29 Go to last post
  2. Using a Cyclone IV to program its own FLASH

    Started by shaiko, Yesterday 11:38
    • Replies: 3
    • Views: 132
    FvM
    Yesterday, 19:06 Go to last post
  3. VHDL How to use TFP401 on a daughter card

    Started by yttuncel, 30th January 2015 15:55
    • Replies: 9
    • Views: 194
    Yesterday, 17:39 Go to last post
  4. software for altera fpga's

    Started by ep.hobbyiest, 17th January 2015 11:54
    • Replies: 13
    • Views: 384
    Yesterday, 10:05 Go to last post
    • Replies: 10
    • Views: 350
    Yesterday, 02:27 Go to last post
  5. Exporting wave in QuestaSim

    Started by bilal_oct, 30th January 2015 18:25
    • Replies: 2
    • Views: 107
    Yesterday, 00:40 Go to last post
  6. Computer architecture help

    Started by Jason12345, 29th January 2015 19:09
    • Replies: 14
    • Views: 206
    30th January 2015, 17:11 Go to last post
  7. 0in_cdc on VHDL/Verilog Designs

    Started by sharath666, 30th January 2015 11:08
    • Replies: 0
    • Views: 87
    30th January 2015, 11:08 Go to last post
    • Replies: 1
    • Views: 51
    30th January 2015, 09:10 Go to last post
  8. COnformal Ultra LVR (final SPICE netlist)

    Started by nohj_yar, 30th January 2015 01:51
    • Replies: 1
    • Views: 60
    30th January 2015, 03:19 Go to last post
  9. spartan 3e usage guide

    Started by mrarslanahmed, 29th January 2015 08:31
    • Replies: 3
    • Views: 118
    30th January 2015, 00:02 Go to last post
  10. need help ,verilog code for Program counter ?

    Started by vead, 28th January 2015 06:43
    • Replies: 14
    • Views: 305
    29th January 2015, 22:11 Go to last post
  11. Leading one detector

    Started by vijaykulkarni, 29th January 2015 19:07
    • Replies: 2
    • Views: 74
    29th January 2015, 20:25 Go to last post
  12. SDF errors in Gate Level simulation :Questasim

    Started by vineethsukumar, 29th January 2015 10:18
    • Replies: 0
    • Views: 84
    29th January 2015, 10:18 Go to last post
  13. [SOLVED] VHDL simulation: $display vs report

    Started by LatticeSemiconductor, 28th January 2015 16:16
    • Replies: 2
    • Views: 151
    29th January 2015, 10:18 Go to last post
  14. need help with filter (VHDL)

    Started by Hui2, 28th January 2015 10:11
    • Replies: 0
    • Views: 51
    28th January 2015, 10:11 Go to last post
  15. Matrix Multiplication in Vhdl

    Started by Eddy786, 22nd January 2015 09:14
    • Replies: 8
    • Views: 268
    27th January 2015, 21:12 Go to last post
  16. how to resolve problem of metastability

    Started by smiley_09, 26th January 2015 17:41
    • Replies: 8
    • Views: 216
    27th January 2015, 11:02 Go to last post
    • Replies: 2
    • Views: 121
    27th January 2015, 09:42 Go to last post
  17. research domains in FPGA

    Started by qne, 27th January 2015 07:42
    • Replies: 0
    • Views: 65
    qne
    27th January 2015, 07:42 Go to last post
  18. modelsim log appending #

    Started by meir, 26th January 2015 11:31
    • Replies: 2
    • Views: 129
    26th January 2015, 19:20 Go to last post
  19. [SOLVED] Design is NOT on-the-fly during Partial Reconfiguration ! Why?

    Started by msdarvishi, 26th January 2015 07:15
    • Replies: 6
    • Views: 163
    26th January 2015, 18:25 Go to last post
  20. wireless communication with FPGA

    Started by Argoth, 24th January 2015 19:16
    • Replies: 5
    • Views: 218
    26th January 2015, 16:47 Go to last post
    • Replies: 1
    • Views: 98
    FvM
    26th January 2015, 11:16 Go to last post
  21. [SOLVED] ERROR [PACK 1105] in PlanAhead

    Started by msdarvishi, 25th January 2015 04:14
    • Replies: 2
    • Views: 141
    25th January 2015, 18:48 Go to last post
  22. Calling VHDL procedures

    Started by shaiko, 25th January 2015 14:37
    • Replies: 2
    • Views: 137
    25th January 2015, 15:17 Go to last post
  23. Randomication in verilog

    Started by shrikanthke, 24th January 2015 10:13
    • Replies: 2
    • Views: 161
    24th January 2015, 16:29 Go to last post
  24. Partial Reconfiguration via ICAP

    Started by msdarvishi, 24th January 2015 01:46
    • Replies: 2
    • Views: 144
    24th January 2015, 16:25 Go to last post
  25. FPGA Design, Digital Clock

    Started by action taker, 23rd January 2015 15:03
    • Replies: 12
    • Views: 282
    23rd January 2015, 23:44 Go to last post
  26. vhdl coding for finding image centroid

    Started by ann mary, 19th January 2015 19:25
    • Replies: 6
    • Views: 350
    23rd January 2015, 20:09 Go to last post

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