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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 16,606
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 23,992
    21st March 2007, 21:21 Go to last post
  1. Implementing logic in ram

    Started by NovNov, 25th April 2017 16:10
    • Replies: 10
    • Views: 230
    Yesterday, 23:23 Go to last post
  2. Help on timing closure

    Started by LatticeSemiconductor, Yesterday 10:13
    • Replies: 4
    • Views: 135
    Yesterday, 22:58 Go to last post
    • Replies: 3
    • Views: 59
    Yesterday, 18:24 Go to last post
  3. Ram accessing through VHDL code.

    Started by abhijithr1, Yesterday 08:27
    • Replies: 2
    • Views: 107
    Yesterday, 11:49 Go to last post
    • Replies: 0
    • Views: 90
    Yesterday, 05:09 Go to last post
  4. Flip Flop Memory in FPGA: Read Write Ports

    Started by dzafar, Yesterday 00:38
    • Replies: 1
    • Views: 92
    Yesterday, 01:04 Go to last post
  5. Generate 40 Hz from 44MHz clock

    Started by dhan_pow, 21st April 2017 05:33
    • Replies: 3
    • Views: 208
    26th April 2017, 16:16 Go to last post
  6. using if statement in verilog

    Started by emerson_11, 21st April 2017 05:22
    • Replies: 7
    • Views: 311
    26th April 2017, 14:20 Go to last post
  7. [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    Started by roshan12, 19th April 2017 05:39
    • Replies: 5
    • Views: 402
    26th April 2017, 07:25 Go to last post
  8. [SOLVED] [moved] Embedded Memory Blocks in FPGA

    Started by dzafar, 25th April 2017 06:43
    • Replies: 1
    • Views: 198
    26th April 2017, 00:19 Go to last post
  9. [SOLVED] vhdl FSM lockout, lazy approach to fix

    Started by wesleytaylor, 24th April 2017 14:13
    • Replies: 7
    • Views: 261
    25th April 2017, 23:27 Go to last post
  10. CD4033 higher input frequency variant?

    Started by neazoi, 25th April 2017 12:24
    • Replies: 4
    • Views: 166
    25th April 2017, 22:15 Go to last post
  11. axi4-stream inetrface

    Started by viyaaloth, 25th April 2017 06:09
    • Replies: 2
    • Views: 128
    25th April 2017, 08:35 Go to last post
    • Replies: 4
    • Views: 159
    25th April 2017, 05:30 Go to last post
  12. Stereo AC97 Audio Codec

    Started by Tarunfpga1, 23rd April 2017 09:48
    • Replies: 6
    • Views: 431
    24th April 2017, 19:41 Go to last post
  13. VHDL 2x16 LCD module

    Started by rmadd95, 20th April 2017 21:01
    • Replies: 4
    • Views: 306
    24th April 2017, 15:44 Go to last post
  14. communication with pc fro fpga

    Started by dipin, 8th April 2017 08:40
    • Replies: 5
    • Views: 491
    24th April 2017, 09:12 Go to last post
  15. understanding the memory specifications

    Started by sai_shashi, 23rd April 2017 06:42
    • Replies: 2
    • Views: 127
    23rd April 2017, 07:54 Go to last post
    • Replies: 1
    • Views: 126
    23rd April 2017, 07:52 Go to last post
  16. [SOLVED] If or else if? Which is better?

    Started by FecP, 22nd April 2017 12:26
    • Replies: 3
    • Views: 275
    22nd April 2017, 19:58 Go to last post
  17. Formal port/generic is not declared error - VHDL

    Started by arve9066, 21st April 2017 19:38
    • Replies: 3
    • Views: 303
    21st April 2017, 22:44 Go to last post
  18. VHDL - generate signals from other signals

    Started by arve9066, 14th April 2017 18:27
    • Replies: 8
    • Views: 582
    21st April 2017, 19:58 Go to last post
    • Replies: 2
    • Views: 186
    20th April 2017, 19:15 Go to last post
  19. How FPGAs are refreshing the logic

    Started by Vlad., 20th April 2017 09:14
    • Replies: 2
    • Views: 260
    20th April 2017, 14:31 Go to last post
  20. [SOLVED] Enumeration of range type - vhdl

    Started by wesleytaylor, 7th April 2017 18:13
    • Replies: 2
    • Views: 273
    20th April 2017, 08:31 Go to last post