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Threads 1 to 30 of 20877

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 03:22
    • Replies: 2
    • Views: 13,302
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 20,815
    21st March 2007, 21:21 Go to last post
  1. Replicated logic optimization

    Started by rac70, Yesterday 09:42
    • Replies: 5
    • Views: 60
    Yesterday, 22:05 Go to last post
  2. [SOLVED] vhdl coding test vectors for pipe lining

    Started by vishushru, Yesterday 13:44
    • Replies: 1
    • Views: 36
    Yesterday, 21:18 Go to last post
    • Replies: 0
    • Views: 51
    Yesterday, 19:01 Go to last post
  3. What is nios ii? (Altera DE0)

    Started by omerysmi, Yesterday 15:53
    • Replies: 2
    • Views: 41
    Yesterday, 16:08 Go to last post
  4. [SOLVED] how to read data from a ddr3 sdram?

    Started by hamidkavianathar, 28th June 2016 06:46
    • Replies: 14
    • Views: 286
    Yesterday, 07:13 Go to last post
  5. Unable to understand a LCD module controller code :(

    Started by hobbyiclearner, 7th June 2016 18:44
    2 Pages
    1 2
    • Replies: 34
    • Views: 792
    22nd July 2016, 18:45 Go to last post
  6. how to find the phase of the signal in fft??

    Started by sandy3129, 14th July 2016 20:15
    • Replies: 7
    • Views: 206
    22nd July 2016, 18:13 Go to last post
  7. Xilinx HDMI 2.0 IP license error

    Started by beginner_EDA, 21st July 2016 14:09
    • Replies: 5
    • Views: 92
    22nd July 2016, 17:02 Go to last post
  8. AXI FIFO does not work

    Started by u24c02, 21st July 2016 02:15
    • Replies: 1
    • Views: 90
    22nd July 2016, 04:00 Go to last post
    • Replies: 0
    • Views: 80
    21st July 2016, 22:10 Go to last post
  9. BPSK mapper for OFDM modulation

    Started by Kosyas41, 20th July 2016 12:13
    • Replies: 3
    • Views: 81
    21st July 2016, 16:45 Go to last post
  10. Using WHEN command during Portmap

    Started by sreevenkjan, 20th July 2016 10:33
    • Replies: 13
    • Views: 168
    21st July 2016, 16:16 Go to last post
  11. Methods of opening a file in VHDL

    Started by shaiko, 18th July 2016 21:58
    • Replies: 17
    • Views: 207
    21st July 2016, 13:30 Go to last post
  12. timing constraints in Vivado

    Started by Sunayana Chakradhar, 19th July 2016 09:47
    • Replies: 5
    • Views: 84
    19th July 2016, 21:34 Go to last post
  13. [SOLVED] timing problem in doing CLOCK DOMAIN CROSSING

    Started by achaleus, 7th July 2016 10:26
    • Replies: 8
    • Views: 222
    19th July 2016, 14:21 Go to last post
  14. Memory read is too late

    Started by Binomex, 18th July 2016 08:18
    • Replies: 5
    • Views: 131
    19th July 2016, 06:38 Go to last post
  15. Generating 150MHz external clock for ml605

    Started by mrmsh, 16th July 2016 07:02
    • Replies: 9
    • Views: 201
    18th July 2016, 12:37 Go to last post
  16. Sharing my 2D convolution filter

    Started by shaiko, 18th July 2016 10:16
    • Replies: 0
    • Views: 82
    18th July 2016, 10:16 Go to last post
    • Replies: 2
    • Views: 68
    17th July 2016, 21:52 Go to last post
  17. Generating Signal Tap "out of context"

    Started by shaiko, 17th July 2016 12:48
    • Replies: 4
    • Views: 72
    FvM
    17th July 2016, 15:08 Go to last post
  18. UART Receiver in VHDL

    Started by arve9066, 15th July 2016 19:57
    • Replies: 4
    • Views: 139
    15th July 2016, 23:38 Go to last post
    • Replies: 4
    • Views: 95
    15th July 2016, 12:32 Go to last post
  19. Modelsim - strange problem with partial assignments

    Started by shaiko, 14th July 2016 11:47
    • Replies: 16
    • Views: 255
    15th July 2016, 09:52 Go to last post
    • Replies: 2
    • Views: 154
    15th July 2016, 01:28 Go to last post
  20. 3 valve controller with CPLD

    Started by manush30, 14th July 2016 09:57
    • Replies: 5
    • Views: 101
    14th July 2016, 16:29 Go to last post
  21. Clock Phase Shift in ALTPLL IP

    Started by sreevenkjan, 24th May 2016 16:27
    • Replies: 10
    • Views: 276
    FvM
    14th July 2016, 09:34 Go to last post
    • Replies: 9
    • Views: 368
    14th July 2016, 09:20 Go to last post
  22. Moved: How to implement LMS algorithm in vhdl?

    Started by Anwesa Roy, 14th July 2016 10:20
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  23. [SOLVED] Verilog parameters used in port dimensions

    Started by wesleytaylor, 13th July 2016 10:40
    • Replies: 1
    • Views: 102
    13th July 2016, 14:14 Go to last post
  24. FIR IP core dosen't work properly

    Started by mohsen68sh, 8th July 2016 16:28
    • Replies: 10
    • Views: 260
    13th July 2016, 12:31 Go to last post

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