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Threads 1 to 30 of 19968

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 03:22
    • Replies: 2
    • Views: 8,944
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 16,193
    21st March 2007, 21:21 Go to last post
  1. Current HDL support for fixed point

    Started by shaiko, Today 10:46
    • Replies: 7
    • Views: 86
    Today, 18:51 Go to last post
  2. Direct assignment to matrix in Verilog.

    Started by ismailov-e, 19th June 2015 06:14
    • Replies: 6
    • Views: 167
    Today, 17:04 Go to last post
    • Replies: 4
    • Views: 90
    K-J
    Today, 16:32 Go to last post
  3. 2D matrix input in VHDL for FFT

    Started by shan14, 3rd June 2015 09:25
    • Replies: 18
    • Views: 457
    Today, 11:28 Go to last post
  4. FPGA Power On Reset Circuit Actel AX2000

    Started by rhnrgn, Yesterday 18:49
    • Replies: 4
    • Views: 94
    Today, 09:29 Go to last post
    • Replies: 5
    • Views: 107
    Today, 08:33 Go to last post
    • Replies: 1
    • Views: 63
    Yesterday, 18:11 Go to last post
  5. VHDL Simulation problem

    Started by MSAKARIM, 29th June 2015 17:26
    • Replies: 16
    • Views: 235
    Yesterday, 17:31 Go to last post
  6. microblaze implementation on fpga,

    Started by moein0114, 1st July 2015 22:43
    • Replies: 3
    • Views: 103
    Yesterday, 16:13 Go to last post
  7. DFF chain using a for loop

    Started by shaiko, 30th June 2015 21:44
    2 Pages
    1 2
    • Replies: 20
    • Views: 271
    FvM
    Yesterday, 14:11 Go to last post
    • Replies: 11
    • Views: 186
    1st July 2015, 23:51 Go to last post
    • Replies: 4
    • Views: 122
    1st July 2015, 16:55 Go to last post
    • Replies: 12
    • Views: 210
    1st July 2015, 16:34 Go to last post
  8. [SOLVED] CRC for SENT Protocol

    Started by ctzof, 29th June 2015 21:47
    • Replies: 5
    • Views: 146
    1st July 2015, 12:35 Go to last post
    • Replies: 1
    • Views: 83
    1st July 2015, 07:05 Go to last post
    • Replies: 7
    • Views: 191
    1st July 2015, 04:49 Go to last post
    • Replies: 3
    • Views: 108
    30th June 2015, 18:45 Go to last post
  9. [SOLVED] FIFO o/p frequency getting reduced by 2

    Started by rahdirs, 30th June 2015 10:15
    • Replies: 3
    • Views: 97
    30th June 2015, 16:15 Go to last post
  10. Metastability in FPGAs

    Started by Tapojyoti Mandal, 30th June 2015 14:59
    • Replies: 1
    • Views: 86
    30th June 2015, 15:42 Go to last post
  11. interface FPGA to GPMC

    Started by M Subash, 30th June 2015 07:34
    • Replies: 4
    • Views: 136
    K-J
    30th June 2015, 14:11 Go to last post
    • Replies: 11
    • Views: 167
    30th June 2015, 09:57 Go to last post
  12. Bidirectional LVDS at Altera Cyclone III

    Started by Saires, 25th June 2015 09:03
    • Replies: 10
    • Views: 235
    FvM
    30th June 2015, 09:44 Go to last post
    • Replies: 2
    • Views: 92
    30th June 2015, 09:22 Go to last post
  13. Altera Avalon ST packet transfer

    Started by shaiko, 24th June 2015 13:38
    • Replies: 16
    • Views: 224
    30th June 2015, 07:57 Go to last post
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  14. Strange behavior of Altera FIFO

    Started by shaiko, 25th June 2015 11:36
    • Replies: 14
    • Views: 183
    29th June 2015, 16:23 Go to last post
  15. IP CORE Creation for FPGA

    Started by Rajalakshmi.E, 26th June 2015 10:01
    • Replies: 5
    • Views: 168
    29th June 2015, 03:19 Go to last post
    • Replies: 2
    • Views: 92
    28th June 2015, 10:57 Go to last post
  16. Interface problem between FPGA and aurduino

    Started by MSAKARIM, 24th June 2015 09:32
    • Replies: 3
    • Views: 141
    28th June 2015, 02:59 Go to last post
  17. VHDL code for 8-bit synchronous reset register

    Started by manojsainadh, 27th June 2015 19:56
    • Replies: 1
    • Views: 96
    27th June 2015, 20:48 Go to last post

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