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Threads 1 to 30 of 18987

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 03:22
    • Replies: 2
    • Views: 6,058
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 13,531
    21st March 2007, 21:21 Go to last post
    • Replies: 0
    • Views: 39
    Today, 07:20 Go to last post
    • Replies: 0
    • Views: 42
    Today, 04:25 Go to last post
    • Replies: 2
    • Views: 103
    Yesterday, 20:28 Go to last post
    • Replies: 1
    • Views: 89
    Yesterday, 14:55 Go to last post
    • Replies: 6
    • Views: 127
    Yesterday, 14:19 Go to last post
  1. Synthesizable Character in VHDL

    Started by Junus2012, 30th September 2014 20:20
    • Replies: 3
    • Views: 135
    Yesterday, 13:00 Go to last post
  2. meaning of timescale 1ns/1ps?

    Started by Vimalab, Yesterday 07:10
    • Replies: 1
    • Views: 70
    Yesterday, 07:41 Go to last post
    • Replies: 0
    • Views: 52
    Yesterday, 02:38 Go to last post
  3. help: real-time applications implemented in FPGA

    Started by zilch, 28th September 2014 13:31
    • Replies: 6
    • Views: 234
    Yesterday, 02:29 Go to last post
  4. [SOLVED] Tool to change a file from synth to simulation values

    Started by wesleytaylor, 30th September 2014 10:31
    • Replies: 5
    • Views: 101
    30th September 2014, 16:08 Go to last post
  5. [SOLVED] problem with nonblocking assignment

    Started by dipin, 26th September 2014 12:34
    • Replies: 6
    • Views: 230
    30th September 2014, 12:25 Go to last post
  6. Why Verilog $fread Only Read til 1658 Byte?

    Started by jasonkee111, 29th September 2014 04:07
    • Replies: 2
    • Views: 127
    30th September 2014, 10:03 Go to last post
    • Replies: 2
    • Views: 150
    30th September 2014, 06:35 Go to last post
  7. nearly accurate counter with VHDL

    Started by mohammadmother, 28th September 2014 15:54
    • Replies: 4
    • Views: 186
    29th September 2014, 23:50 Go to last post
  8. ternary content addressable memory vs SRAM memory

    Started by mahalakshmi r, 28th September 2014 11:16
    • Replies: 6
    • Views: 121
    29th September 2014, 18:26 Go to last post
  9. Verilog Code Is Not Producings The Expected Results

    Started by luyunfei330, 28th September 2014 17:58
    • Replies: 3
    • Views: 140
    29th September 2014, 18:21 Go to last post
  10. How to give power to SIM908 Antenna

    Started by Amalinda, 10th June 2013 02:15
    • Replies: 10
    • Views: 636
    29th September 2014, 10:11 Go to last post
    • Replies: 11
    • Views: 216
    28th September 2014, 12:37 Go to last post
  11. spartan 3e starter UDP IP ethernet VHDL

    Started by mckr, 26th September 2014 09:55
    • Replies: 18
    • Views: 279
    27th September 2014, 20:42 Go to last post
  12. multiply Matrix in VHDL

    Started by mothermohammad, 23rd September 2014 11:17
    • Replies: 2
    • Views: 124
    27th September 2014, 08:27 Go to last post
  13. tcam memory implement in sram architecture

    Started by mahalakshmi r, 26th September 2014 19:13
    • Replies: 1
    • Views: 103
    26th September 2014, 22:03 Go to last post
    • Replies: 3
    • Views: 138
    26th September 2014, 21:45 Go to last post
  14. Procedural Assignment error (verilog )

    Started by vead, 23rd September 2014 06:42
    2 Pages
    1 2
    • Replies: 32
    • Views: 610
    26th September 2014, 18:28 Go to last post
  15. low frequency clocks generation in xilinx clock wizard

    Started by kommu4946, 12th September 2014 17:06
    • Replies: 9
    • Views: 345
    26th September 2014, 16:02 Go to last post
    • Replies: 12
    • Views: 304
    26th September 2014, 15:24 Go to last post
    • Replies: 0
    • Views: 59
    26th September 2014, 07:36 Go to last post
  16. Fix error in this Verilog code

    Started by prakhars, 24th September 2014 13:16
    • Replies: 15
    • Views: 305
    25th September 2014, 21:30 Go to last post
    • Replies: 7
    • Views: 218
    25th September 2014, 20:01 Go to last post
  17. Differential signals as single ended connection

    Started by AWahab, 24th September 2014 13:22
    • Replies: 16
    • Views: 277
    25th September 2014, 14:32 Go to last post
  18. [SOLVED] Regarding : Post synthesis simulation

    Started by verylsi, 24th September 2014 09:43
    • Replies: 8
    • Views: 172
    25th September 2014, 05:18 Go to last post

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