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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 15,255
    2nd June 2013, 17:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 22:21
    • Replies: 0
    • Views: 22,723
    21st March 2007, 22:21 Go to last post
    • Replies: 1
    • Views: 22
    Today, 13:41 Go to last post
    • Replies: 2
    • Views: 155
    Today, 09:50 Go to last post
  1. FFT core design on FPGA board

    Started by mohamed_shfat, 12th January 2017 19:25
    • Replies: 12
    • Views: 388
    Today, 09:43 Go to last post
    • Replies: 5
    • Views: 176
    FvM
    Yesterday, 19:25 Go to last post
  2. PRBS output values vhdl

    Started by Kosyas41, Yesterday 13:23
    • Replies: 3
    • Views: 176
    Yesterday, 14:51 Go to last post
  3. Protected Registered PAL REV ENG

    Started by apprenticemart2, 20th September 2016 15:34
    • Replies: 10
    • Views: 478
    14th January 2017, 22:54 Go to last post
  4. Moved: FFT and FIFO synchronization in FPGA

    Started by mohamed_shfat, 14th January 2017 17:54
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  5. I am new to NIOS II. Need help for my requirement.

    Started by niks, 7th January 2017 01:33
    • Replies: 4
    • Views: 306
    14th January 2017, 05:25 Go to last post
  6. [SOLVED] Analizing a VHDL program code

    Started by Janoy66, 11th January 2017 10:56
    • Replies: 13
    • Views: 410
    13th January 2017, 20:33 Go to last post
  7. Need a suggestion for SoC Communication References

    Started by ammar_kurd, 9th January 2017 06:56
    • Replies: 2
    • Views: 236
    13th January 2017, 20:02 Go to last post
  8. ISE 14.6 - iMPACT crashes everytime it starts

    Started by pigtwo, 7th January 2017 23:29
    • Replies: 3
    • Views: 239
    13th January 2017, 12:23 Go to last post
  9. Transceiver and SDI Interface

    Started by beginner_EDA, 22nd December 2016 12:07
    • Replies: 8
    • Views: 449
    13th January 2017, 10:07 Go to last post
  10. LFSR reverse function

    Started by LatticeSemiconductor, 11th January 2017 12:02
    • Replies: 5
    • Views: 320
    12th January 2017, 19:06 Go to last post
  11. KC705 FPGA Board LCD Screen control

    Started by macellan, 12th January 2017 11:36
    • Replies: 4
    • Views: 253
    12th January 2017, 15:20 Go to last post
  12. Request for hardware test

    Started by omidrey, 11th January 2017 11:43
    • Replies: 8
    • Views: 295
    11th January 2017, 22:26 Go to last post
  13. [VHDL NEXYS 3] new to this language, need help

    Started by jacksparrow93, 7th January 2017 15:32
    • Replies: 7
    • Views: 320
    10th January 2017, 23:36 Go to last post
  14. Moved: To route data from one SDI Channel to another

    Started by beginner_EDA, 13th January 2017 09:54
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    • Replies: 3
    • Views: 223
    9th January 2017, 23:22 Go to last post
  15. VHDL 1 D Kalman Filter

    Started by abimann, 8th January 2017 10:58
    • Replies: 7
    • Views: 295
    FvM
    9th January 2017, 15:05 Go to last post
  16. ALTCLKCTRL vs PLL with 2 reference clocks

    Started by shaiko, 8th January 2017 23:52
    • Replies: 0
    • Views: 220
    8th January 2017, 23:52 Go to last post
  17. VHDL: 'open' ports assignment

    Started by muhammad_ali, 2nd January 2017 10:40
    • Replies: 4
    • Views: 277
    7th January 2017, 13:46 Go to last post
  18. Verilog HDL line following module

    Started by xinhui, 7th January 2017 08:13
    • Replies: 1
    • Views: 232
    7th January 2017, 10:23 Go to last post
  19. how to interface ADC7656 with altera max

    Started by panimalar, 5th January 2017 11:15
    • Replies: 6
    • Views: 178
    6th January 2017, 13:02 Go to last post
  20. a help to write a sample timer code

    Started by MohamadStark, 5th January 2017 17:41
    • Replies: 3
    • Views: 250
    6th January 2017, 06:41 Go to last post
  21. lms algorithm code in vhdl

    Started by alok_das_gupta, 5th January 2017 13:29
    • Replies: 2
    • Views: 200
    5th January 2017, 15:25 Go to last post
  22. [SOLVED] help in verilog code

    Started by dipin, 26th December 2016 07:42
    • Replies: 4
    • Views: 336
    4th January 2017, 06:02 Go to last post
    • Replies: 14
    • Views: 355
    4th January 2017, 04:31 Go to last post
  23. camera interface with FPGA

    Started by emerson_11, 2nd January 2017 04:50
    • Replies: 9
    • Views: 333
    3rd January 2017, 18:18 Go to last post
  24. Lattice ICE40HX8K unresponsive when programed

    Started by salmanmahmood, 28th December 2016 17:35
    • Replies: 9
    • Views: 342
    3rd January 2017, 13:17 Go to last post
  25. stuck at faults implementation using FPGA

    Started by guru2kiot, 2nd January 2017 10:10
    • Replies: 3
    • Views: 285
    3rd January 2017, 09:32 Go to last post

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