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Threads 301 to 330 of 21746

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] doubt in sdc file ....

    Started by dipin, 31st March 2017 13:18
    • Replies: 1
    • Views: 222
    31st March 2017, 14:31 Go to last post
  2. synchronized serial data capture to registers

    Started by sharak, 30th March 2017 07:51
    • Replies: 5
    • Views: 245
    31st March 2017, 06:49 Go to last post
  3. [SOLVED] SPI protocol on MAX10

    Started by rayhh27, 30th March 2017 14:33
    • Replies: 2
    • Views: 195
    30th March 2017, 15:43 Go to last post
    • Replies: 2
    • Views: 225
    30th March 2017, 11:03 Go to last post
  4. DDR3 maximum current rating

    Started by viyaaloth, 29th March 2017 08:20
    • Replies: 1
    • Views: 222
    29th March 2017, 22:55 Go to last post
  5. Maximum/ typical current rating for each FPGA bank

    Started by viyaaloth, 28th March 2017 11:03
    • Replies: 6
    • Views: 376
    29th March 2017, 16:57 Go to last post
  6. XST giving wrong/unrelated errors...bug?

    Started by whack, 27th March 2017 02:03
    • Replies: 13
    • Views: 375
    28th March 2017, 16:01 Go to last post
  7. current rating for CPLD

    Started by viyaaloth, 28th March 2017 11:11
    • Replies: 1
    • Views: 221
    28th March 2017, 15:27 Go to last post
    • Replies: 2
    • Views: 328
    28th March 2017, 08:09 Go to last post
    • Replies: 4
    • Views: 388
    26th March 2017, 05:03 Go to last post
    • Replies: 1
    • Views: 249
    25th March 2017, 10:57 Go to last post
    • Replies: 5
    • Views: 349
    25th March 2017, 06:39 Go to last post
  8. VHDL - native log2 and ceil for value 1

    Started by shaiko, 24th March 2017 22:31
    • Replies: 2
    • Views: 409
    25th March 2017, 01:08 Go to last post
    • Replies: 5
    • Views: 258
    24th March 2017, 14:30 Go to last post
    • Replies: 2
    • Views: 227
    24th March 2017, 09:33 Go to last post
  9. Problems with Verilog bit array.....

    Started by PhillHS, 20th March 2017 02:23
    • Replies: 3
    • Views: 291
    24th March 2017, 06:57 Go to last post
  10. Xilinx Spartan 6 - Use PLL to create 1 MHz clock

    Started by pigtwo, 21st March 2017 03:29
    • Replies: 17
    • Views: 706
    23rd March 2017, 23:10 Go to last post
    • Replies: 5
    • Views: 403
    23rd March 2017, 15:05 Go to last post
  11. Srio ipcore. can't simulate when using 3.125g mode.

    Started by bravoegg, 21st March 2017 12:01
    • Replies: 2
    • Views: 297
    22nd March 2017, 16:01 Go to last post
  12. Manually implementation of a FIR filter in a FPGA.

    Started by flote21, 14th March 2017 17:42
    • Replies: 16
    • Views: 613
    22nd March 2017, 09:36 Go to last post
    • Replies: 16
    • Views: 504
    20th March 2017, 20:56 Go to last post
  13. how to write a verilog code using point form??

    Started by yeppolife92, 17th March 2017 08:38
    • Replies: 7
    • Views: 397
    20th March 2017, 16:14 Go to last post
  14. [SOLVED] MIG FIFO Requirement

    Started by pcmistic, 18th March 2017 15:35
    • Replies: 2
    • Views: 331
    19th March 2017, 12:56 Go to last post
    • Replies: 1
    • Views: 325
    17th March 2017, 10:39 Go to last post
  15. newbie's questions about PAL

    Started by dk_spb, 24th February 2017 17:40
    • Replies: 18
    • Views: 536
    15th March 2017, 10:51 Go to last post
    • Replies: 9
    • Views: 425
    15th March 2017, 10:35 Go to last post
    • Replies: 4
    • Views: 450
    15th March 2017, 10:26 Go to last post