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Threads 301 to 330 of 21460

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 1
    • Views: 354
    19th November 2016, 10:56 Go to last post
    • Replies: 3
    • Views: 227
    18th November 2016, 11:04 Go to last post
  1. syncronize output signal

    Started by franticEB, 17th November 2016 00:30
    • Replies: 11
    • Views: 291
    18th November 2016, 04:01 Go to last post
    • Replies: 3
    • Views: 275
    17th November 2016, 22:45 Go to last post
  2. Power measurement on FPGA-Xc3s4000-FG676

    Started by Wesley90, 10th November 2016 12:27
    • Replies: 13
    • Views: 313
    17th November 2016, 19:13 Go to last post
  3. To shift half clock data

    Started by beginner_EDA, 17th November 2016 13:43
    • Replies: 3
    • Views: 259
    17th November 2016, 17:07 Go to last post
  4. [SOLVED] Weird Verilog testbench behavior!

    Started by redsees, 16th November 2016 20:47
    • Replies: 3
    • Views: 251
    17th November 2016, 07:16 Go to last post
  5. xilinx interlever ipcore not working?

    Started by bravoegg, 17th November 2016 01:49
    • Replies: 0
    • Views: 221
    17th November 2016, 03:06 Go to last post
  6. JTAG buffer chip for Altera FPGAs

    Started by sherif123, 13th November 2016 15:59
    • Replies: 6
    • Views: 385
    16th November 2016, 15:48 Go to last post
  7. Timing Analysis in FPGA

    Started by Ravindrakant Jha, 13th November 2016 09:48
    • Replies: 8
    • Views: 422
    16th November 2016, 06:26 Go to last post
    • Replies: 5
    • Views: 313
    16th November 2016, 01:34 Go to last post
    • Replies: 5
    • Views: 278
    FvM
    15th November 2016, 18:24 Go to last post
  8. MIPS interoptive processor FPGA compatibility.....

    Started by velu.plg, 14th November 2016 16:59
    • Replies: 15
    • Views: 350
    15th November 2016, 18:17 Go to last post
  9. Microsemi, Microprocessor subsystems

    Started by Morell, 6th November 2016 18:35
    • Replies: 6
    • Views: 414
    15th November 2016, 16:57 Go to last post
  10. [SOLVED] Running parallel RAM at a different clock than CPU?

    Started by Artlav, 14th November 2016 00:52
    • Replies: 6
    • Views: 308
    14th November 2016, 20:05 Go to last post
  11. Why is the fitter pruning registers

    Started by Nanoprotect, 14th November 2016 06:35
    • Replies: 4
    • Views: 269
    14th November 2016, 16:49 Go to last post
  12. comparing values of 2 memory locations

    Started by p11, 13th November 2016 17:01
    • Replies: 10
    • Views: 346
    14th November 2016, 16:36 Go to last post
    • Replies: 6
    • Views: 317
    FvM
    14th November 2016, 09:51 Go to last post
  13. Moved: Microsemi, Microcontroller subsystems

    Started by Morell, 13th November 2016 20:37
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  14. benchmark C code for 8 bit RISC-based Miro-controller

    Started by ahmad.sb101, 12th November 2016 11:56
    • Replies: 1
    • Views: 266
    13th November 2016, 17:25 Go to last post
  15. verilog converts real into an integer

    Started by lh-, 11th November 2016 12:40
    • Replies: 12
    • Views: 329
    lh-
    11th November 2016, 16:55 Go to last post
    • Replies: 0
    • Views: 231
    11th November 2016, 13:09 Go to last post
  16. [SOLVED] quartus pin assignments problem

    Started by dipin, 10th November 2016 06:40
    • Replies: 11
    • Views: 415
    11th November 2016, 12:29 Go to last post
  17. Spartan 3E Digital Clock Manager Problem

    Started by newbie123FPGA, 10th November 2016 22:45
    • Replies: 1
    • Views: 209
    10th November 2016, 22:59 Go to last post
  18. [Verilog]ALTIOBUF - Output must drive top level pin

    Started by pigtwo, 8th November 2016 03:58
    • Replies: 14
    • Views: 530
    10th November 2016, 09:48 Go to last post
  19. tracking the rising_edge of 2 clocks

    Started by p11, 9th November 2016 18:09
    • Replies: 7
    • Views: 261
    10th November 2016, 00:42 Go to last post
  20. concat operator in verilog

    Started by lh-, 9th November 2016 12:53
    • Replies: 7
    • Views: 274
    9th November 2016, 14:54 Go to last post
  21. VHDL: how to avoid latches

    Started by Rorsh14, 8th November 2016 12:00
    • Replies: 6
    • Views: 322
    8th November 2016, 15:53 Go to last post
  22. How does one verify timing constraints?

    Started by matrixofdynamism, 1st November 2016 10:53
    • Replies: 9
    • Views: 394
    8th November 2016, 11:43 Go to last post
  23. SPI interface Vivado/SDK

    Started by beginner_EDA, 24th October 2016 13:09
    2 Pages
    1 2
    • Replies: 25
    • Views: 1,111
    8th November 2016, 09:55 Go to last post

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