zero width pulse problem?

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rettylee

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Hi,guys:
when I wrote a simple alway block,the 0 width pulse problem came out..

always@(posedge clk) begin
a = $random;
end
always@(negedge clk) begin
b = $random;
end

But saw the waveform ,I found that the sometimes a and b changed at the same time.There is a "0" width pulse in "clk".Anyone can tell me how to remove the "0" width pulse from the "clk" signal ?
Thanks for your help....
 

what is "clk" connected to. my guess is that you have some other issues. inertial delays might work, but most likely you've generated "clk" from some expression where a term gets updated which causes clk to go to 1 AND starts the evaluation of a process that updates another term, causing clk to go to 0.
 

The "clk" came from analog behavior model with multi_driver....Maybe the problem is from there.But now I could not rewrite the analog behavior model ,is there any method to remove the "0" width pulse?
 

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