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Zero in Common sourse amplifer

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hjzs18

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Hi, all;

suppose i have a garden-variaty common source amplifer , and also suppose i put a Miller compensation cap,say Cc , between the drain and gate, now i add a zero to my system and the value is Gm/Cc, i wonder if anybody here can give me an intuitive explaination why it is this form.how to think of it.

in Razavi's book, he gives a explaination, it is something about current flowing back from the output. but i just can not get it


Thanks all
 

hjzs18

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Hi, Can anybody here help me understand that?
 

JT

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An easy way of looking at it :

The miller capacitor provides a (frequency dependend) forward path to the output.
So you can see the miller cap together with the impedance of the output transistor as high pass filter, with C = Cmiller and R = 1/gm.

This will give a zero at :

z = 1/(Cmiller* 1/gm)

This zero will cause that the transistor is no longer effective and does not inverse anymore.
 

hjzs18

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Thank you JT, but how come the resistance is 1/Gm, i know the resistance looking into the source is 1/gm, and when the transistor is diode connected, the resistance is also 1/gm , but this time i am looking into the gate , am i right? since this is a amplifying transistor.

can u explain it more thoroughly?
BTW, can u explain why a high pass filter can give me a zero? that is ,at that frequency,even though maybe not attainable, i am getting a zero output?

thanks alot
 

ambreesh

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HI hjzs18,

Are you also having a load capacitance connected from drain of source follower to gnd.
 

hjzs18

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ambreesh said:
HI hjzs18,

Are you also having a load capacitance connected from drain of source follower to gnd.
Hi Ambreesh:

actually , i just use one common source amplifier,and it is basically a thought expreriment.

I dont not think the load capacitance is relevent to the question, since when at zero frequency(although it is not attainabel actually), the output is Zero due to the definition of "Zero", and any load will see a short there. So it is a characteristic of system, and the load has nothing to do with it, am i right, or some flaw in my logic?

actually, u can see from the expression of the zero value. it is nothing but gm/Cgd or gm/Cc.

Thanks Ambreesh.
 

ambreesh

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Hi,

The definition of zero as i understand is that frequency where the forward gain due to both the forward paths (as in our case) add upto zero.
You have asked how does gm come into picture, as I understand.
So if we add up the gains through both the paths equate it to zero, we would get the frequecy of zero. Which turns out to be gm/Cc.
As this frequency is very high, the cap Cc more or lessappears to be short and the gate appears to be connected to drain. More or less a MOS in diode connected configuration.
Why do you say that zero frequency is not attainable, it is a function of capacitance between gate and drain.?
This in pratical circuits adds a RHZ that spoils the phase margin, if the frequency as you suggest if unattinable, it should not effect the phase margin at all?
The load shorting at zero frequency is a function of the capacitance at that node, In a thought experiment that could be far smaller than Cc?
 

liuyonggen_1

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ambreesh said:
Hi,

The definition of zero as i understand is that frequency where the forward gain due to both the forward paths (as in our case) add upto zero.
You have asked how does gm come into picture, as I understand.
So if we add up the gains through both the paths equate it to zero, we would get the frequecy of zero. Which turns out to be gm/Cc.
As this frequency is very high, the cap Cc more or lessappears to be short and the gate appears to be connected to drain. More or less a MOS in diode connected configuration.
Why do you say that zero frequency is not attainable, it is a function of capacitance between gate and drain.?
This in pratical circuits adds a RHZ that spoils the phase margin, if the frequency as you suggest if unattinable, it should not effect the phase margin at all?
The load shorting at zero frequency is a function of the capacitance at that node, In a thought experiment that could be far smaller than Cc?

i think so .if the load is a capacitor ,the resistance of the diode-connected transistor will be gm//c-load rather than gm
could you tell me your e-mail ,i would like to ask you some questions if necessary
my e-mai is liuyonggen_1@163.com
 

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