xst problem
well you have written a very high level code, thats way its taking time. ireg is written in very high-level description, that might also causing problem. split the design into datapath and control-unit. draw a datapath block diagram of your core -- showing alu, register file, temp-regs, data_ram and code-rom, muxes (where needed) and their interconnection -- in other words for rtl think in terms these components. then draw controller fsm -- which will generate control signals.
other issues are avoid type "bit", "bit_vector" use "std_logic" & "std_logic_vector" instead, as it not suitable for both simulation & synthesis. avoid shared variables, use signals.
see these cores (links below) as well, first one is very good quality.
see books like "vhdl coding style" by ben cohen (see coding for synthesis), "Digital Logic and Microprocessor Design with VHDL" by Enoch Hwang,
"vhdl programming by example" by Douglas Perry, "rapid prototyping of digital systems" by hamblen and furman. and comp-arch book like "computer orginization hardware/software interface" by hennesy and patterson. (some of these books are on edaboard).
FYI
www.oregano.at/ip/ip01.htm
www.opencores.org/projects.cgi/web/8051
(hope this helps!)