Xst:737 - Found 1-bit latch for signal <SIG_bit>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Architecture SIGNAL SIG_bit : STD_LOGIC := '0'; TYPE state IS (init, load_nx_block, load_pixel, generate_bs, no_block_check); BEGIN CASE pr_state IS WHEN generate_bs => SIG_bit <= SIG(SIG_addr); IF p_count = 0 THEN IF (dout >= threshold) AND (SIG_bit = '0') THEN stream <= "10"; ELSIF (dout >= threshold) AND (SIG_bit = '1') THEN stream <= "01"; ELSE stream <= "00"; END IF; nx_state <= no_block_check; ELSE IF (dout >= threshold) AND (SIG_bit = '0') THEN stream <= "10"; ELSIF (dout >= threshold) AND (SIG_bit = '1') THEN stream <= "01"; ELSE stream <= "00"; END IF; nx_state <= load_pixel; END IF;
Can you please tell me where to make necessary changes, so that the warning is removed?
The answer is given in the warning message.
If you anyone else to debug your code, you have to post the entire code. You code shows only 1 state 'generate_bs'.
You need to post the entire code, not just the snippet, as this doesnt show the problem - which will be that SIG_bit is not assigned in every state.
I got the reason for the warning, ads-ee is right, i had assigned SIG_bit only in this state. So I have to assign it in all states with some value.I suspect the only place that SIG_bit is assigned is in the generate_bs state, which is why the OP only posted that snippet of code.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ram_FSM is generic ( ADDR_WIDTH : integer := 8; DATA_WIDTH : integer := 8; N : INTEGER := 16); -- N x N image size Port ( clk : in STD_LOGIC; we : out STD_LOGIC; din : in unsigned(DATA_WIDTH-1 downto 0); dout : out unsigned(DATA_WIDTH-1 downto 0); address : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0); stream: out STD_LOGIC_VECTOR(1 downto 0));-- 00 means 0, 01 => 1, 10 => 10, 11 => no output -- output 0 => pixel insig, 1 => pixel significant, 10 => pixel significant and positive end ram_FSM; architecture Behavioral of ram_FSM is -- SPIHT SIGNALS -- SIGNAL BL : STD_LOGIC_VECTOR(N*N/4-1 downto 0);-- N*N/8 block locations need to be initialized SIGNAL SIG : STD_LOGIC_VECTOR(N*N-1 downto 0):= (OTHERS => '0'); SIGNAL threshold : UNSIGNED(7 downto 0) := "10000000"; SIGNAL BL_addr : INTEGER RANGE 0 TO N*N/4-1 := 0; SIGNAL PX_addr,p1_addr : INTEGER RANGE 0 TO N*N-1 := 0; SIGNAL str : STD_LOGIC_VECTOR(1 downto 0); -- FSM SIGNALS -- TYPE state IS (init, load_nx_block, load_pixel, bs_generate, no_block_check); SIGNAL pr_state, nx_state, var_state : state; SIGNAL p_count: INTEGER RANGE 0 to 3 := 0; CONSTANT one : STD_LOGIC_VECTOR(7 downto 0) := "00000001"; begin -- with pr_state select -- p_count <= p_count + 1 when bs_generate -- p_count when others; -- with pr_state ----- FSM STARTS FROM HERE ---- -- Lower Section of FSM -- lower:PROCESS(clk) BEGIN IF clk'EVENT AND clk = '1' THEN pr_state <= nx_state; END IF; END PROCESS lower; -- INITIALIZATION -- l3: PROCESS(nx_state,p_count) BEGIN IF nx_state = init THEN BL(N*N/64-1 downto 0) <= (OTHERS => '1'); END IF; END PROCESS l3; -- PIXEL ADDRESS GENERATOR -- l1:PROCESS(nx_state,p_count,BL_addr) BEGIN IF nx_state = load_pixel THEN IF p_count = 0 THEN p1_addr <= 4*BL_addr; ELSIF p_count = 1 THEN p1_addr <= 4*BL_addr + 1; ELSIF p_count = 2 THEN p1_addr <= 4*BL_addr + 2; ELSE p1_addr <= 4*BL_addr + 3; END IF; END IF; END PROCESS l1; -- BITSTREAM GENERATOR -- l2:PROCESS(nx_state,p_count,din,threshold,SIG) BEGIN IF nx_state = bs_generate THEN if (din >= threshold) AND (SIG(p1_addr) = '0') then str <= "10"; dout <= din - threshold; SIG(p1_addr) <= '1'; elsif (din >= threshold) AND (SIG(p1_addr) = '1') then str <= "01"; dout <= din - threshold; SIG(p1_addr) <= '1'; else str <= "00"; end if; END IF; END PROCESS l2; -- Upper Section of FSM -- upper:PROCESS(pr_state, p_count,p1_addr,str,BL) -- VARIABLE out_count : INTEGER RANGE 0 TO 9 := 0; BEGIN CASE pr_state IS WHEN init => BL_addr <= 0; nx_state <= load_nx_block; WHEN load_nx_block => BL_addr <= BL_addr + 1; p_count <= 0; if BL(BL_addr) = '1' then nx_state <= load_pixel; else nx_state <= load_nx_block; end if; WHEN load_pixel => address <= std_logic_vector(to_unsigned(p1_addr,ADDR_WIDTH)); we <= '0'; nx_state <= bs_generate; WHEN bs_generate => if p_count = 3 then p_count <= 0; stream <= str; nx_state <= no_block_check; else p_count <= p_count + 1; stream <= str; nx_state <= load_pixel; end if; we <= '1'; WHEN no_block_check => if BL_addr >= N*N/4-1 then nx_state <= init; else nx_state <= load_nx_block; end if; END CASE; END PROCESS upper; end Behavioral;
Same Warning for all SIG_0 to SIG_255Xst:737 - Found 8-bit latch for signal <address>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 8-bit latch for signal <dout>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <SIG_255>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
entity warningcheck is
Port ( clk : in STD_LOGIC);
end warningcheck;
architecture Behavioral of warningcheck is
SIGNAL SIG : STD_LOGIC_VECTOR(31 downto 0):= (OTHERS => '0');
SIGNAL SIG_addr : INTEGER RANGE 0 TO 31 := 0;
TYPE state IS (init, exit1);
SIGNAL pr_state, nx_state : state;
begin
-- PROCESS FOR GENERATING SIG_addr --
count : PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF SIG_addr >= 31 THEN
SIG_addr <= 0;
ELSE
SIG_addr <= SIG_addr + 1;
END IF;
END IF;
END PROCESS count;
-- Lower Section of FSM --
lower : PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
pr_state <= nx_state;
END IF;
END PROCESS lower;
-- Upper Section of FSM --
upper : PROCESS(pr_state)
BEGIN
CASE pr_state IS
WHEN init =>
SIG(SIG_addr) <= '1';
nx_state <= exit1;
WHEN exit1 =>
SIG(SIG_addr) <= '0';
nx_state <= init;
END CASE;
END PROCESS upper;
end Behavioral;
Can anybody tell me how to assign all bits of signal SIG and at the same time keep them unaffected?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 process (clk, rst) begin if (rst = '1') then -- stuff to reset elsif (rising_edge(clk)) then -- all the code goes in this section, and I mean all of it: FSM, outputs, everything. end if; end process;
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