Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enabl

[ketanlad_18]

hi,i am writing the code for right shift.it is synthesis without error.but several warnings are generated.warnings are stated after code.please give me idea to remove this error.

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity fl1 is
  generic ( wE : positive := 6;
            wF : positive := 13 );
  port ( clk: in std_logic;
         rst: in std_logic;
            nA : in  std_logic_vector(wE+wF downto 0);
         nB : in  std_logic_vector(wE+wF downto 0);
         nR : out std_logic_vector(wE+wF downto 0));
end fl1;
 
architecture Behavioral of fl1 is
 
signal nA_e,nB_e: std_logic_vector(wE-1 downto 0):=(others=>'0');
signal nA_f,nB_f: std_logic_vector(wF-1 downto 0):=(others=>'0');
signal n_diff_i:integer range 0 to 255:=0;
signal sign,c:std_logic:='0';
signal si:std_logic:='0';
signal s : STD_LOGIC_VECTOR (12 downto 0):=(others=>'0');
signal dsum:std_logic_vector(wF-1 downto 0):=(others=>'0');
 
type state is (zero,one,two,three);
type state1 is (a1,a2,a3);
signal co:state1;   
signal comb:state;
 
begin
p1:process(clk,rst,nA,nB,nB_f,nA_F,nA_e,nB_e,si,comb)
 
begin
 
if rst='1' then
   comb<=zero;
elsif rst='0' and clk='1' and (nA(wE+wF-1 downto wF)=nB(wE+wF-1 downto wF)) then
   comb<=one;
elsif rst='0' and clk='1' and (nA(wE+wF-1 downto wF)>nB(wE+wF-1 downto wF))then
   comb<=two;
elsif rst='0' and clk='1' and (nA(wE+wF-1 downto wF)<nB(wE+wF-1 downto wF))then
   comb<=three;
else comb<=zero;
end if;
   
case comb is
  when zero=>
       si<='0';
       nA_e<=(others=>'0');
         nB_e<=(others=>'0');
       nA_f<=(others=>'0');
       nB_f<=(others=>'0');      
  when one=>
       if nA(wF-1 downto 0)> nB(wF-1 downto 0) then
                si<=nA(wE+wF);
         elsif nA(wF-1 downto 0)< nB(wF-1 downto 0) then
                si<=nB(wE+wF);
       else si<=nA(wE+wF);      
         end if;
        
       nA_e<=nA(wE+wF-1 downto wF);
         nB_e<=nB(wE+wF-1 downto wF);
         nA_f(wF-1 downto 0)<=nA(wF-1 downto 0);
         nB_f<=nB(wF-1 downto 0);
  
  when two=>         
          nA_e(wE-1 downto 0)<=nA(wE+wF-1 downto wF);
         nA_f(wF-1 downto 0)<=nA(wF-1 downto 0);
          nB_e(wE-1 downto 0)<=nB(wE+wF-1 downto wF);
         nB_f(wF-1 downto 0)<=nB(wF-1 downto 0);
          si<=nA(wE+wF);
  
  when three=>  
         nA_e(wE-1 downto 0)<=nB(wE+wF-1 downto wF);
         nA_f(wF-1 downto 0)<=nB(wF-1 downto 0);
          nB_e(wE-1 downto 0)<=nA(wE+wF-1 downto wF);
         nB_f(wF-1 downto 0)<=nA(wF-1 downto 0);
         si<=nB(wE+wF);
  
  when others=>
        nA_e(wE-1 downto 0)<=(others=>'0');
         nA_f(wF-1 downto 0)<=(others=>'0');
          nB_e(wE-1 downto 0)<=(others=>'0');
         nB_f(wF-1 downto 0)<=(others=>'0');
          si<='0';
            
end case;
 
end process p1;
 
p2:process(clk,n_diff_i,nA_e,nB_e,s,co,rst,nB_f)
begin
  n_diff_i<=conv_integer(nA_e-nB_e);
 
if rst='1'   then co<=a1;
elsif rst='0'  and  clk='1' then
    if n_diff_i=0 then co<=a2;
    elsif n_diff_i>0  and n_diff_i<13 then
          co<=a3;
    else co<=a1;
    end if;    
else 
 
     co<=a1;
    end if;
 
case co is
    when a1=>s<="0000000000000";
     when a2=>s(12 downto 0)<=nB_f;
     when a3=>--s<="1111111111111";
             s(12 downto 12-n_diff_i)<=(OTHERS =>'0');      
                s(12-n_diff_i+1 downto 0) <= '1'& nB_f(12 downto n_diff_i);
     
     when others=>s<="0000000000000";
     end case;
 
end process p2;
end Behavioral;

---

warnings

WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:737 - Found 1-bit latch for signal <s_7>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_8>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_9>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_10>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_11>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_12>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_0>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_1>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_2>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_3>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_4>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_5>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_6>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

 

[TrickyDicky]

you havent followed the template for synchronous design. Hence you build a load of logic (and no registers.

I suggest following this template for synchronours design:

process(clk, reset) --ONLY clk and reset
begin
  if reset = '1' then
    --do async reset here
  elsif rising_edge(clk) then
    --register descriptions go here
  end if;
end process;

 

[ketanlad_18]

hi,thanks for suggestion
i replaced following portion of code.

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Code VHDL - [expand]
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p2:process(clk,n_diff_i,nA_e,nB_e,s,co,rst,nB_f)
begin
n_diff_i<=conv_integer(nA_e-nB_e);
 
if rst='1' then co<=a1;
elsif rst='0' and clk='1' then
if n_diff_i=0 then co<=a2;
elsif n_diff_i>0 and n_diff_i<13 then
co<=a3;
else co<=a1;
end if;
else
 
co<=a1;
end if

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replaced portion:

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Code VHDL - [expand]
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p2:process(clk,rst,n_diff_i,nA_e,nB_e,s,co,nB_f)
begin
  n_diff_i<=conv_integer(nA_e-nB_e);
 
if rst='1' then co<=a1;
--elsif   clk='1' then
--    if rst='1' then co<=a1;
elsif  rising_edge(clk) then
    if n_diff_i=0 then co<=a2;
       elsif n_diff_i>0  and n_diff_i<13 then
            co<=a3;
       else co<=a1;
       end if;
end if;

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but therse is also some warnings as follows:

Using one-hot encoding for signal <comb>.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:737 - Found 1-bit latch for signal <s_7>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_8>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_9>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_10>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_11>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_12>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_0>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_1>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_2>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_3>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_4>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_5>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <s_6>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.

pls,suggest for these warnings