Hello,
in my VHDL code for VGA interface i am making output of three colours, red,green and blue. I decided to generate some colour, which will always be displayed on the screen.
here is a code for the final AND gates which will output the colour signal:
Code:
RED_AND: AND_3
GENERIC MAP(8)
PORT MAP ( I0 => h_data_on,
I1 => v_data_on,
I2 => "11011000", -- 11011000
O => r_out);
now i want to register this signals with D flip flop (since this signal will leave the FPGA chip, it must be registered)
Code:
RED_REGISTER: dffn
GENERIC MAP(8)
PORT MAP ( Clock => Clk,
reset => Res,
ckena => '1',
d => r_out,
q => r_outf);
the same code is for other two colours.
well syntach check process goes good. But during the synthesizing i get the following Warnings:
Code:
WARNING:Xst:1710 - FF/Latch <q_0> (without init value) has a constant value of 0 in block <RED_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_1> (without init value) has a constant value of 0 in block <RED_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_2> (without init value) has a constant value of 0 in block <RED_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_5> (without init value) has a constant value of 0 in block <RED_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_0> (without init value) has a constant value of 0 in block <GREEN_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_1> (without init value) has a constant value of 0 in block <GREEN_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_5> (without init value) has a constant value of 0 in block <GREEN_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_7> (without init value) has a constant value of 0 in block <GREEN_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_1> (without init value) has a constant value of 0 in block <BLUE_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_2> (without init value) has a constant value of 0 in block <BLUE_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_4> (without init value) has a constant value of 0 in block <BLUE_REGISTER>.
WARNING:Xst:1710 - FF/Latch <q_5> (without init value) has a constant value of 0 in block <BLUE_REGISTER>.
WARNING:Xst:1710 - FF/Latch <BLUE_REGISTER/q_5> (without init value) has a constant value of 0 in block <VGActrl>.
and the following infos:
Code:
Xst:2261 - The FF/Latch <BLUE_REGISTER/q_7> in Unit <VGActrl> is equivalent to the following 11 FFs/Latches, which will be removed : <BLUE_REGISTER/q_6> <BLUE_REGISTER/q_3> <BLUE_REGISTER/q_0> <GREEN_REGISTER/q_6> <GREEN_REGISTER/q_4> <GREEN_REGISTER/q_3> <GREEN_REGISTER/q_2> <RED_REGISTER/q_7> <RED_REGISTER/q_6> <RED_REGISTER/q_4> <RED_REGISTER/q_3>
Xst:2261 - The FF/Latch <BLUE_REGISTER/q_5> in Unit <VGActrl> is equivalent to the following 11 FFs/Latches, which will be removed : <BLUE_REGISTER/q_4> <BLUE_REGISTER/q_2> <BLUE_REGISTER/q_1> <GREEN_REGISTER/q_7> <GREEN_REGISTER/q_5> <GREEN_REGISTER/q_1> <GREEN_REGISTER/q_0> <RED_REGISTER/q_5> <RED_REGISTER/q_2> <RED_REGISTER/q_1> <RED_REGISTER/q_0>
as you see...all the warnings deal with RED_REGISTER block..
so, the flip flops are created, which never flip or never flop...
i know..its because i assigned constant values right?
Will the synthesizer will totally remove my output signals? or it just removes non used flip flops...and constantly feeds constant signal?
and my quetion is:
Can i ignore these warnings and still put my final synthesized code on the Virtex2 pro FPGA chip, connect monitor and see what it shows?
thanks