[SOLVED] XOR using only one 2:1 MUX, without using any NOT, OR, AND, etc gates

[imbichie]

Hi All,

Is there anyone know, how to make the XOR gate using only one 2:1 MUX.

This is a question asked by an interviewer.

If we have a NOT gate and a 2:1 MUX then we can make it easily, but how we can make hte same with only 2:1 MUX

 

[barry]

I'm not sure this can be done. I looked at it a little bit, but couldn't figure it out. I'd be interested to see it done. You can do it with 2 mux's or mux and gate.

 

[shatruddha]

Well if you do not have a restriction on number of mux to be used, i think you can cascade two mux and use one mux as a not gate.

take two 2:1 mux U1 and U2. For U1 for I0 connect it to logic 1 and I1 to logic 0. For select bit use S1. Connect output of U1 to I1 of U2, I0 to S1 and select bit to S0. (S0 is lower bit say 'a' and S1 is 'b'). With this you can implement XOR using 2:1 MUX.
BTW was it LSI interview??

 

[barry]

Well if you do not have a restriction on number of mux to be used, i think you can cascade two mux and use one mux as a not gate.

take two 2:1 mux U1 and U2. For U1 for I0 connect it to logic 1 and I1 to logic 0. For select bit use S1. Connect output of U1 to I1 of U2, I0 to S1 and select bit to S0. (S0 is lower bit say 'a' and S1 is 'b'). With this you can implement XOR using 2:1 MUX.
BTW was it LSI interview??

You've nicely answered a totally different question. The op was asking to do this with "only one" mux.

 

[syedshan]

I think it was only using MUX , but we can use multiple MUXes...But restriction is not to use any other gates.

But I am also interested the solution. I saw tried but could not figure out the answer

 

[barry]

I think this is a trick question. The interviewer is just trying to see if he can make you cry.

 

[mrflibble]

If you have the inverted version of one of the 2 inputs as well then yes, otherwise it's coffee time. Or maybe it's one of those "lets see how pedantic our candidate can be" questions...

 

[syedshan]

but even if u have the inverted version, means you have used NOT gate...so coffee time option looks better

 

[mrflibble]

but even if u have the inverted version, means you have used NOT gate...so coffee time option looks better

Not at all. As with all "fun riddles", it's not a matter of problem solving skills, it's a matter of full on pedantics. XD

I suppose the main reason for such a question is to check if the interviewee will tell you to bugger off, just like in a real design situation. Anyways, in the classical sense of "I will cooperate with your poorly formulated riddle" with inputs A and B and a single 2:1 mux ... there is no solution.

Crap proof:
- take inputs A=1, B=1
- there is no logic inversion element available anywhere within our riddle universe, yet we require an output of 0
- there is no static 0 or 1 value available either in our riddle universe, because riddles generate vacuum that way
- we require a 0 output, yet no 0 value exists in our universe
- universe implodes
- the end

But I do agree that coffee is a much better way to spend time than waste it on "fun riddles"

 

[imbichie]

Thanks guys for clarifying that there is no solution for the riddles which make me feel that we are having good taste for coffee...

 

[shatruddha]

Actually I was asked the same question once in my LSI interview, I asked him if there is restriction on number of MUX he said no, so I gave him that solution.