reg cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7;
always @(posedge wb_clk_i)
begin
if (wb_we_i = 1'b0)
case (wb_adr_i) // synopsis parallel_case
3'b000: cs0 <= 1'b1;
3'b001: cs1 <= 1'b1;
3'b010: cs2 <= 1'b1;
3'b011: cs3 <= 1'b1; // write is transmit register (txr)
3'b100: cs4 <= 1'b1; // write is command register (cr)
3'b101: cs5 <= 1'b1;
3'b110: cs6 <= 1'b1;
3'b111: cs7 <= 1'b1; // reserved
endcase
else
begin
cs0 <= 1'b0;
cs1 <= 1'b0;
cs2 <= 1'b0;
cs3 <= 1'b0;
cs4 <= 1'b0;
cs5 <= 1'b0;
cs6 <= 1'b0;
cs0 <= 1'b0;
end
end
bufif1 buf0[8:0] ( wb_dat_o, prer[ 7:0], cs0);
bufif1 buf1[8:0] ( wb_dat_o, prer[15:8], cs1);
bufif1 buf2[8:0] ( wb_dat_o, ctr, cs2);
bufif1 buf3[8:0] ( wb_dat_o, rxr , cs3);
bufif1 buf4[8:0] ( wb_dat_o, sr , cs4);
bufif1 buf5[8:0] ( wb_dat_o, txr , cs5);
bufif1 buf6[8:0] ( wb_dat_o, cr , cs6);
bufif1 buf7[8:0] ( wb_dat_o, 8'h0 , cs7);