Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Xilinx xc9572xl instead of Altera epm7064

Status
Not open for further replies.

ulaska

Member level 3
Joined
Aug 25, 2005
Messages
54
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,790
Hello, i have some problems.

in a microcontroller circuit, we use CPLD between the CPU bus and I/O Device bus.

we use reference design circuit, and we use xilinx xc9572xl-10 , instead of altera epm7064 - 7..
but our xilinx doesnt work, it works but not all functions..

can be any problem with the Time issue, cause altera is 7ns, our xilinx is 10 ns.
does it matter a lot?
we dont use any global clocks GCK or etc..

our inputs are IORD# IOWR# OE# WR# ... from CPU..

the problem is not very clearly, sorry, if you want i can attach the PLD circuit.

thank you.
 

ulaska

Member level 3
Joined
Aug 25, 2005
Messages
54
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,790
Xilinx xc9572xl instead of @ltera epm7064

ok i forget to explain that i use ISE 7.1i + sp4
i dont think there is a bug.


we use CPLD between the CPU bus and I/O Device bus.
the problem is: we can see the data bits in the CPU bus line, but we cannot see the necessary data bits in the I/O device data bus (afterwards CPLD)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top