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I see this statement in teh UCF file assigning location E1 to signal data_p
NET "data_p" LOC = "E1" | IOSTANDARD = LVDS_33 ;
but i do not see the location for data_n which is negative differential signal. so where is this assigned ? When I see teh schematics, i see E2 is location where data_n is assigned. how is this happening ?
Added after 1 hours 46 minutes:
I found the answer for this
HDL Instantiation:
Only one input buffer is required to be instantiated in the design and placed on the correct IO_L#P location. The N-side of the buffer will be reserved, and no other IOB is allowed to be placed on this location.
In the physical device, a configuration option is enabled that routes the pad wire from the IO_L#N IOB to the differential input buffer, located in the IO_L#P IOB. The output of this buffer then drives the output of the IO_L#P cell or the input register in the IO_L#P IOB. In FPGA Editor, it will appear that the second buffer is unused. However, any attempt to use this location for another purpose will cause a DRC error in the software.
Ok. So now my question is. can these pins be re-assigned as single ended signals. Is it just that i have to redefine the pins, ex
NET "1" LOC = "D1" | IOSTANDARD = LVCMOS33 ;
NET "2" LOC = "C1" | IOSTANDARD = LVCMOS33 ;
C1 and D1 represent locations IO_L01P_7 and IO_L01N_7
Added after 31 minutes:
well i guess the location IO_LXXY _# XX is number and Y is P/N can be configured as single ended or differntial as per our requirement.....
NET "data_p" LOC = "E1" | IOSTANDARD = LVDS_33 ;
but i do not see the location for data_n which is negative differential signal. so where is this assigned ? When I see teh schematics, i see E2 is location where data_n is assigned. how is this happening ?
Added after 1 hours 46 minutes:
I found the answer for this
HDL Instantiation:
Only one input buffer is required to be instantiated in the design and placed on the correct IO_L#P location. The N-side of the buffer will be reserved, and no other IOB is allowed to be placed on this location.
In the physical device, a configuration option is enabled that routes the pad wire from the IO_L#N IOB to the differential input buffer, located in the IO_L#P IOB. The output of this buffer then drives the output of the IO_L#P cell or the input register in the IO_L#P IOB. In FPGA Editor, it will appear that the second buffer is unused. However, any attempt to use this location for another purpose will cause a DRC error in the software.
Ok. So now my question is. can these pins be re-assigned as single ended signals. Is it just that i have to redefine the pins, ex
NET "1" LOC = "D1" | IOSTANDARD = LVCMOS33 ;
NET "2" LOC = "C1" | IOSTANDARD = LVCMOS33 ;
C1 and D1 represent locations IO_L01P_7 and IO_L01N_7
Added after 31 minutes:
well i guess the location IO_LXXY _# XX is number and Y is P/N can be configured as single ended or differntial as per our requirement.....