Hello every body,
when i was synthesizing a Design with xilinx tool.it showed some error were i am using a two dimentional array ,i think the tool is not able to understand the way the design is been written that's why it's sowing FATAL ERROR
in this lines
The ERROR REPORT is FATAL ERROR( it shows nothing else)
if(count1==2'b00)begin
store[add][63:0]<=lbi_liga_data;
end else if(count1==2'b01)begin
store[add][127:64]<=lbi_liga_data;
end else if(count1==2'b10)begin
store[add][191:128]<=lbi_liga_data;
end else if(count1==2'b11)begin
store[add][255:192]<=lbi_liga_data;
here i am storing data in memory of size{ [255:0]store[1023:0]
here as the data is in burst so it is not possible to use reg instead of Memory.
can you suggest some logic so that the error is fixed during synthesis.
see basically there no need for whole module
and the module is also too large so i can't paste it here
when i am comenting this lines
store[add][63:0]<=lbi_liga_data;
store[add][127:64]<=lbi_liga_data;
store[add][191:128]<=lbi_liga_data;
store[add][255:192]<=lbi_liga_data
the code is synthesized it does't shows any error
or else when i m uncommenting the lines it showed Fatal error
so basically the error is because of this lines only is there any other way
Writing bytes/bits into a 2-dimensional array is hardly supported in any tool . As nand gates suggested go ahead and describe 4/ 2 memories , however you want it and then write into the array. U see there is no hardware which can allow you to write into parts of a memory location. You can use byte selects for selecting the bytes alright but ultimately it gets implemented with multiple memories and byte selects acts as memory select . Hope you get my point
when i am comenting this lines
store[add][63:0]<=lbi_liga_data;
store[add][127:64]<=lbi_liga_data;
store[add][191:128]<=lbi_liga_data;
store[add][255:192]<=lbi_liga_data