Xilinx tool synthesis fatal error

[stay_in_chaos]

Hello every body,
when i was synthesizing a Design with xilinx tool.it showed some error were i am using a two dimentional array ,i think the tool is not able to understand the way the design is been written that's why it's sowing FATAL ERROR
in this lines
The ERROR REPORT is FATAL ERROR( it shows nothing else)
if(count1==2'b00)begin
store[add][63:0]<=lbi_liga_data;
end else if(count1==2'b01)begin
store[add][127:64]<=lbi_liga_data;
end else if(count1==2'b10)begin
store[add][191:128]<=lbi_liga_data;
end else if(count1==2'b11)begin
store[add][255:192]<=lbi_liga_data;
here i am storing data in memory of size{ [255:0]store[1023:0]
here as the data is in burst so it is not possible to use reg instead of Memory.

can you suggest some logic so that the error is fixed during synthesis.

Thanks and regards
stay_in_chaos

 

[echo47]

synthesis error

What is the error message?

Please show a full module, not just a few lines extracted from the middle.

Xilinx ISE (through version 8.1i) does not support two-dimensional arrays.

reg [255:0]store[1023:0] is a one-dimensional array.

XST can infer Block RAM, but only if you write full-width words. Try using four 64-bit wide arrays instead of one 256-bit wide array.

 

[stay_in_chaos]

Re: synthesis error

see basically there no need for whole module
and the module is also too large so i can't paste it here

when i am comenting this lines
store[add][63:0]<=lbi_liga_data;
store[add][127:64]<=lbi_liga_data;
store[add][191:128]<=lbi_liga_data;
store[add][255:192]<=lbi_liga_data

the code is synthesized it does't shows any error
or else when i m uncommenting the lines it showed Fatal error

so basically the error is because of this lines only is there any other way

plz help me

 

[nand_gates]

Re: synthesis error

Why can't you use 4 memories of 64X1024 for store??
Think hardware then use VHDL just to describe it!

 

[semiconductorman]

Re: synthesis error

Writing bytes/bits into a 2-dimensional array is hardly supported in any tool . As nand gates suggested go ahead and describe 4/ 2 memories , however you want it and then write into the array. U see there is no hardware which can allow you to write into parts of a memory location. You can use byte selects for selecting the bytes alright but ultimately it gets implemented with multiple memories and byte selects acts as memory select . Hope you get my point

 

[tkbits]

Re: synthesis error

when i am comenting this lines
store[add][63:0]<=lbi_liga_data;
store[add][127:64]<=lbi_liga_data;
store[add][191:128]<=lbi_liga_data;
store[add][255:192]<=lbi_liga_data

the code is synthesized it does't shows any error

That's because it is equivalent to

store[add][255:0] <= {libi_liga_data[63:0], libi_liga_data[63:0], libi_liga_data[63:0], libi_liga_data[63:0]};

 

[samcheetah]

Re: synthesis error

What is the error message?

Please show a full module, not just a few lines extracted from the middle.

Xilinx ISE (through version 8.1i) does not support two-dimensional arrays.

reg [255:0]store[1023:0] is a one-dimensional array.

XST can infer Block RAM, but only if you write full-width words. Try using four 64-bit wide arrays instead of one 256-bit wide array.

im also having a simillar problem. ISE 8.1i gives me an error if i write

input [2:0] abc [255:0];

actually my input is a one dimensional array. is this supported?

 

[echo47]

synthesis error

input [2:0] abc [255:0];

I don't think Verilog allows arrays in I/O declarations.