Re: Where to start?
The VHDL compiler generates typically a .bit or .jed file (depending on if we are dealing with FPGA or CPLD).
The actual programming is done using the JTAG port of the FPGA/CPLD. For this you, obviously, need a JTAG programmer.
If you have a complete Xilinx development package, including such a JTAG programmer/adapter, then the whole compilation and programming is done from within the ISE.
If you don't use a Xilinx supported JTAG adapter then you have to use the software of your own JTAG adapter, and use the generated .bit/.jed file.
In some case such a development package can include some other means of programming the FPGA/CPLD. You have to check the manual of the development package for this.