erikwikt
Junior Member level 1
XILINX - FPGA clocking problem
Hello. I just want to start with that I'm very new to FPGA design so my knowledge at the time very limited. I'm using the Virtex®-5 XC5VLX110T that is mounted on the XILINX™XUPV5-LX110T development board.
I'm trying to make a "hardware test-bench" for a DDR2 memory controller that I have generated from XILINX MIG 3.61 core generator. Its just a simple state machine that write to some locations in the memory and then reads from them.
The problem that I have now is that I can't really clock the design. When I was generating the memory controller I choose a differential clock design and PLL as clock source which gave me four clock inputs. One 200Mhz and one "user clock" that sets the operating frequency for the memory controller. I have been able to find a clock source for the 200Mhz clock and specified that in my UCF file but I cant find a clock source for the "user clock" that is differential.
I know there is a clock-source on the board that is identified as "USERCLK" that runs in 100Mhz. The two problems with this one is that its single-ended and it only runs in 100Mhz which is to slow for the memory controller since the manual for the controller says that the "user clock" has to be between 125Mhz and 266Mhz.
My first try was then to just route the incoming 200Mhz differential clock signal to both the differential clock pairs on the design, this gave me this following error messages:
If someone could please explain what this messages means that would really be helpful.
Thank you in advance.
-Erik
Hello. I just want to start with that I'm very new to FPGA design so my knowledge at the time very limited. I'm using the Virtex®-5 XC5VLX110T that is mounted on the XILINX™XUPV5-LX110T development board.
I'm trying to make a "hardware test-bench" for a DDR2 memory controller that I have generated from XILINX MIG 3.61 core generator. Its just a simple state machine that write to some locations in the memory and then reads from them.
The problem that I have now is that I can't really clock the design. When I was generating the memory controller I choose a differential clock design and PLL as clock source which gave me four clock inputs. One 200Mhz and one "user clock" that sets the operating frequency for the memory controller. I have been able to find a clock source for the 200Mhz clock and specified that in my UCF file but I cant find a clock source for the "user clock" that is differential.
I know there is a clock-source on the board that is identified as "USERCLK" that runs in 100Mhz. The two problems with this one is that its single-ended and it only runs in 100Mhz which is to slow for the memory controller since the manual for the controller says that the "user clock" has to be between 125Mhz and 266Mhz.
My first try was then to just route the incoming 200Mhz differential clock signal to both the differential clock pairs on the design, this gave me this following error messages:
Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible.
Further explanation:
The component already has an input slave buffer.
Symbols involved:
PAD symbol "clk200_n" (Pad Signal = clk200_n)
SlaveBuffer symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST/SLAVEBUF.DIFFIN" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST/SLAVEBUF.DIFFIN)
SlaveBuffer symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST/SLAVEBUF.DIFFIN" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST/SLAVEBUF.DIFFIN)
Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible.
Further explanation:
The I/O component already owns an input buffer.
Symbols involved:
PAD symbol "clk200_p" (Pad Signal = clk200_p)
DIFFAMP symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST/IBUFDS" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/clk200_ibufg)
DIFFAMP symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST/IBUFDS" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/sys_clk_ibufg)
If someone could please explain what this messages means that would really be helpful.
Thank you in advance.
-Erik
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