library ieee;
use ieee.std_logic_1164.all;
entity Top_Memory_Test is
port (
sys_clk : in std_logic;
....
clk200_p : in std_logic;
clk200_n : in std_logic;
....
);
end Top_Memory_Test;
architecture behavior of Top_Memory_Test is
COMPONENT Top_DCM
PORT(
CLK_IN : IN std_logic;
....
CLK_OUT_P : OUT std_logic;
CLK_OUT_N : OUT std_logic
);
END COMPONENT;
component Memory_SM
.....
end component;
component DDR2_MEM
.....
end component;
signal INTERNAL_sys_clk : std_logic;
signal INTERNAL_sys_clk_p : std_logic;
signal INTERNAL_sys_clk_n : std_logic;
begin -- behavior
INTERNAL_sys_rst_n <= sys_rst_n;
INTERNAL_sys_clk <= sys_clk;
uut: Top_DCM PORT MAP (
CLK_IN => INTERNAL_sys_clk,
RST_IN => INTERNAL_sys_rst_n,
CLK_OUT_P => INTERNAL_sys_clk_p,
CLK_OUT_N => INTERNAL_sys_clk_n
);
MEM_SM : Memory_SM generic map (....) port map (....);
MEM_CTRL : DDR2_MEM generic map (....) port map (
sys_clk_p => INTERNAL_sys_clk_p,
sys_clk_n => INTERNAL_sys_clk_n,
);
end behavior;