I'm using the "Multiplier Generator V7.0" IP Core to calculate the squared magnitude of a complex number a+jb, i.e. I calculate a^2+b^2.
To calculate a^2 and b^2 I use two of the mentioned multiplier cores. When I do a behavioral simulation everything is OK.
When I simulate the placed and routed model, the result is also OK, but shortly before the correct a^2 or b^2 is stable, there are fast changes in the values of a^2 and b^2.
The default Coregen settings are registered input and registered output. Did you change the output to non-registered? That would cause combinatorial wiggling for a few nanoseconds. That's normal, because you are looking at the output of the multiplication logic.
I usually don't bother using that core. I simply put a*a and b*b and some registers into my HDL.
I use Virtex II also. I'm running ISE 6.3i SP3 and Modelsim SE 6.0c.
Yes, a*a is combinatorial. If you want to go fast, add some pipeline registers like in my Verilog example below. PAR says it will go 171 MHz in a 2V80-4. I could push it somewhat faster by using advanced placement constraints.
Code:
module top(clk, y);
input clk; // synthesis attribute period clk "6.0ns";
reg signed [17:0] a=1;
reg signed [35:0] p;
output reg signed [35:0] y;
always @ (posedge clk) begin
a <= {a,a[17]~^a[10]}; // LFSR noise generator
p <= a * a; // ISE uses the multiplier's input register
y <= p; // ISE uses the chip's IOB register
end
endmodule
I don't think I've ever tried the Coregen multiplier. I'll try it and report back a little later.
Well, rats. I can't inspect the Coregen multiplier output because ISE renamed the core's output bus to crazy names and mixed them in with about 500 other crazy names. I can't tell what's what. I rarely do post-route simulation because it's so messy.
How long is your interval of "fast changes"? If it's one or two nanoseconds, then it's probably just the normal routing skew of the 36 bit bus. If you run the bus across the chip, the skew may increase by a few more ns.
I don't know VHDL. In Verilog the "always posedge clk" block defines a section of clocked logic. My example has three ordinary clocked registers: a, p, and y.
Beware that ISE will sometimes move registers around combinatorial logic. For example, if you put several pipeline registers on the output of the multiplier, ISE may move one or two of them to the input side to improves performance. Sometimes ISE moves registers to hurt performance. ISE isn't perfect.
wwahib2 - I think ISE always includes coregen. Try searching your hard drive for coregen.exe. Its directory should be in your path.
Only 0.55 ns? That sounds like a relatively small delay skew among the bus signals. Your signals probably don't travel very far. Each bit takes a slightly different path.
You can use FPGA Editor to view the routes and timing. It's educational, somewhat fun, and occasionally disappointing. In the "List" window, select "Routed Nets", highlight the signals in your bus, and click Tools -> Delay. That will fill in the "Max Pin Delay" column with the path delays. Beats me why it's called "pin delay". You can also sort the list by column - sometimes very useful.
Yes do I see the time variations in my a*a approach. Looks normal.
I discovered something (which I do not understand:
When I start the simulation of the placed and routed design within ISE, I get the mentioned "fast changes". But when I end the simulation and restart it within Modelsim the "fast changes" are gone ??!?? Hää
Can I trust Modelsim/ISE ???
Added after 17 minutes:
FPGA Editor seems to be a nice tool. Is there a tutorial available about this tool.
I'd like to learn more about it.
I don't use Project Manager, so I can't guess what's happening with your ModelSim restarts. It doesn't sound like a ModelSim bug though. More like something sending the wrong files to ModelSim. Which is exactly why I don't use Project Manager - too much hidden activity.
I haven't seen an FPGA Editor tutorial. Just the stuff under "Help".