barry
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Anyone have any experience using this primitive? I've instantiated it, and the FPGA apparently doesn't get configured using Vivado Hardware Manager. (I get a message saying DONE didn't go high). Here's my instantiation, what's wrong?
Code:
startupe2_inst: STARTUPE2
generic map (
PROG_USR => "FALSE", --not secure bitstream
SIM_CCLK_FREQ=> 0.0 --simulation clock
)
port map(
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => SPI_CLK_s, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);