strahd_von_zarovich
Full Member level 2
Hi everyone,
I am designing a board which has Kintex-7 series FPGA and DDR3 ICs on it. The problem is Xilinx Application Note says something like this;
"CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The skew allowed between CK/CK# and DQS/DQS# must be bounded between 0 and 1,600 ps. The recommended skew between CK/CK# and DQS DQS# is 150 ps to 1,600 ps for components/UDIMMs and for RDIMMs it is 450 ps to 750 ps. For DIMM modules, the total CK/CK# and DQS/DQS# propagation delays from the FPGA to the memory components on the DIMM must be accounted for when designing to this requirement."
"CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. " This line is okay. But at least 150ps is too much, this forces me to make all address, control and clock signal lines much more longer. Am I missing something?
Thanks in advance.
Canberk
I am designing a board which has Kintex-7 series FPGA and DDR3 ICs on it. The problem is Xilinx Application Note says something like this;
"CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The skew allowed between CK/CK# and DQS/DQS# must be bounded between 0 and 1,600 ps. The recommended skew between CK/CK# and DQS DQS# is 150 ps to 1,600 ps for components/UDIMMs and for RDIMMs it is 450 ps to 750 ps. For DIMM modules, the total CK/CK# and DQS/DQS# propagation delays from the FPGA to the memory components on the DIMM must be accounted for when designing to this requirement."
"CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. " This line is okay. But at least 150ps is too much, this forces me to make all address, control and clock signal lines much more longer. Am I missing something?
Thanks in advance.
Canberk
