Hello,
I generated a fir filter using IP coregen, but when trying to build the bitstream I get timing constraints errors and a lot of wires are left unconnected.
This happens if if set the filter's clock frequency at 200Mhz(250Mhz is max in the coregen window) and use a DCM to double my board frequency(from 100 to 200MHz).
If I set the filter's clock frequency at 100Mhz it works without any problems,but the number of resources occupied doubles and I cant really afoard that on the long run because I will be using a lot of filters.
I also mention that the core generator's settings are set to match my fpga board. I can't understand why this happens since core gen tells me that the maximum frequency allowed is 250 MHz, and since I can create a bitstream which contains 5 filters running at 100Mhz(each occupying almost double the resources of a filter running at 200MHz ).
I find it odd, given the things mentioned above, that I cant implement a DCM and a filter running at 200MHz.
Thank you,
Benton