angilberto
Newbie
dds xilinx
I'm able to "generate" the core (dds and/or nco) but when I instantiate it, it seems to be not connected.
I mean, if I check the schematic view everything seems to be ok.
I am able to run the simulation but the output of "my" dds/nco is always ZERO!
I cant see the error on my code (yeah, it probably is obvious...)
Thanks
Angilberto.
------------
thats my code:
I'm able to "generate" the core (dds and/or nco) but when I instantiate it, it seems to be not connected.
I mean, if I check the schematic view everything seems to be ok.
I am able to run the simulation but the output of "my" dds/nco is always ZERO!
I cant see the error on my code (yeah, it probably is obvious...)
Thanks
Angilberto.
------------
thats my code:
Code:
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//dds YourInstanceName (
// .CLK(CLK),
// .SINE(SINE));
`timescale 1ns / 1ps
module ddsdac(clk, dac);
input clk;
output dac;
reg [5:0] dac;
wire [5:0] sine;
dds dds1 (
.CLK(clk),
.SINE(sine));
always @(posedge clk)
//assign dac = sine;
dac <= sine;
endmodule
//
A tiny little bit of some warning messages:
WARNING:Simulator:12 - Port CLK of module C_MUX_BIT_V7_0 in instance
/ddsdac/dds1/BU257/MSBmux/ is left unconnected....
...
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