Xilinx IO Constraints

[dkk1980]

Hi all,



The OFFSET constraint does not optimize paths clocked by an internally generated clock.

We have an external input clock of 50 Mhz, which is divided by a DCM internally to generate a 25 Mhz clock. The internal logic works with 25Mhz clock.

How do we apply the OFFSET constraints?



If our requirement is 10 ns AFTER 25 Mhz clock RISING, then with respect to the 50Mhz what should be the value that has to be applied ? 20 ns ? 5 ns ?



Thanks



dkk

 

[gongdori]

Hm... I am not really sure, but shouldn't it be the same since the edge of half rate clock aligns with the 1x clock?
Below talks about the offset constraint and shows some examples...

https://www.xilinx.com/support/documentation/white_papers/wp237.pdf

 

[jimwu88]

What clock is used for the device that receives the data from the FPGA?

Hi all,



The OFFSET constraint does not optimize paths clocked by an internally generated clock.

We have an external input clock of 50 Mhz, which is divided by a DCM internally to generate a 25 Mhz clock. The internal logic works with 25Mhz clock.

How do we apply the OFFSET constraints?



If our requirement is 10 ns AFTER 25 Mhz clock RISING, then with respect to the 50Mhz what should be the value that has to be applied ? 20 ns ? 5 ns ?



Thanks



dkk

 

[dkk1980]

hi thanks for the reply.

What clock is used for the device that receives the data from the FPGA? -- 25 Mhz Internally generated clock