xilinx fpga router error,can someone heip me?

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shoufeng_luo

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Hello everyone, I use a pair of LVDS signals as the differential clks of DCM,When implementing the design ,I encounter an error as follow:This design contains an LVDS pair.The pair of IOs must be palced in a specific relatice structure.What should I do to correct the error?Thanks !
 

Place pins correctly! There must be some guidelines in Xilinx's documentation for your FPGA refered to "PCB Layout" or "Pad Placement & DC Guidelines". For example, Altera's Cyclone have such restrictions:

- Single-ended inputs may be only be placed four or more pads away from a differential pad.
- Single-ended outputs and bidirectional pads may only be placed five or more pads away from a differential pad.
 

you are in big problem since they are dedicated pins (you probebly using GC).

the only solution i see is to use the clock as single ended clock signal.
 

Thanks a lot,a pair of differential signals should be connected to a pair of differential pads of fpga.But I connect them to two pads not be a pair.So the error happens.I obliged to use a sigle ended colck.
 

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