Xilinx FPGA post simulation

[nemolee]

Dear Sir,

I have questions about Spartan 3A FPGA post simulation.
Can I believe the result of FPGA postsim?
I check the postsim waveform and find a cell (XBUF) inserted by PAR tool between output PAD and the latest FF. This XBUF is not expected.
And cell delay is so large.
How should I do to delete this XBUF?
Thank you very much.

 

[echo47]

The post-route simulation is usually very accurate.

I've never heard of an XBUF.

Try opening the routed chip in FPGA Editor, and examine the output pad to see exactly what happened.

Maybe you simply need to apply the "IOB" option or constraint. It allows an output flop to be placed into an IOB. However, that may not work well if your flop's output feeds back into the design.

 

[lubee]

Firstly,you should check the rules that allows an output flop to be placed into an IOB and check whether your design comply with these rules.

And then,maybe you can modify the attributes of the output ports,some of which can reduce the time delay.

good luck!

 

[nemolee]

Thank you everybody.
I tried to set the constraint to my design.
And a good thing happened.
Your opinion is useful for me.