I have a design, which I suspect is being poorly mapped on design, and I would like to place the critical components and let the planahed do the rest.
I already opened the FPGA editor and place the main components (RAM and DSP48), but now I am stuck at this point. Spartan-6 seems not to support autoplace, and I don't know how order the planahead to start the implementation with the placement I already started.
There isn't a build flow in planahead per-se it uses the ISE flow (especially the original versions). Xilinx was trying to incorporate planahead as the entire front end to ISE (they bought the company that made planahead), but that only became a reality in 14.x series of the tools, but I don't recall the exact 14.x version that this happened. So depending on the version of Xilinx tools you're using...you might have planahead bolted onto the side of ISE or you might have a planahead that is embedded in the side of ISE or you might have a planahead that is ISE.
Hmmm, that almost sounds like a space alien species taking over the planet by replacing people movie.
Well, I use the last version 14.7, so it should be the most integrated planahead possible.
In fact, the project was done on ISE and I am testing planahead and its functionality. I miss the possibility of making a partial place-and route or mapping, there is only implementation now.
Well the whole idea behind planahead and now vivado is the ability to partition the design in the GUI and place logic where you want it to go save off the ucf/sdc file...then push the implement button and end up with a design that meets timing and can be immediately downloaded to the board.
If you're using 14.7 then you were probably in the "planahead mode" which means you can't do anything but make area/placement type constraints. I really disliked that GUI "mode" stuff they added. I'd rather have everything available anytime I want.