xilinx fpga area report
I am confused on the area/map utilization report that I got from xilinx project navigator tools and i attached the report below.
(1) Which number is important in this report? What is my actual utilization now? I am planning to add in a few more blocks later. So I need to decide if i need to purchase a larger capacity of the virtex II or not.
(2) In the virtex II datasheet, the XC2V1500 has 1.5M system gates, and in my report, it said the equivalent gate count is 280K. Does that mean I only used 1/5 of the fpga resources? If not, what does these nunbers represent? How many of resources are used for interconnect?
Thanks in advance!
Design Information ------------------
Target Device : x2v1500
Target Package : fg676
Target Speed : -6
Mapper Version : virtex2
-- $Revision: 1.16.8.2 $ Mapped Date : Tue Jan 02 16:04:45 2007
Design Summary --------------
Number of errors: 0
Number of warnings: 20
Logic Utilization:
Number of Slice Flip Flops: 7,115 out of 15,360 46%
Number of 4 input LUTs: 14,346 out of 15,360 93%
Logic Distribution:
Number of occupied Slices: 7,678 out of 7,680 99%
Number of Slices containing only related logic: 6,424 out of 7,678 83%
Number of Slices containing unrelated logic: 1,254 out of 7,678 16%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 14,630 out of 15,360 95%
Number used as logic: 14,346
Number used as a route-thru: 275
Number used as Shift registers: 9
Number of bonded IOBs: 104 out of 392 26%
IOB Flip Flops: 68
Number of Block RAMs: 2 out of 48 4%
Total equivalent gate count for design: 286,651
Additional JTAG gate count for IOBs: 4,992
Peak Memory Usage: 202 MB