Xilinx Device utilization

[dhanya22]

I am doing addition of "A" and "B" in an Adder design,where A and B both are 8 bits each, and I want to know how much resources are utilized in terms of Slices, etc in Xilinx for different simulations.i.e if i do addition of 1 bit, how much actual devices are used.
Can I get the count in Xilinx ?

 

[TrickyDicky]

Yes.
Write the code - compile it, and check the compilation reports.

 

[dhanya22]

I have written a single code for eight bit addition, compiled it but what I need is that for different bit addition's (i.e 1 bit, 2 bit, 3 b..) I need separate device utilization summary, using same code.Is it possible ?

 

[TrickyDicky]

If you wrote an 8 bit addition, then thats what you'll get the summary for.
You will have to modify the code to see the utilisation for 1bit, 2bit etc.

 

[ads-ee]

Use a parameter or generic to modiy the width of the arguments and result. Then set it to a nee value on each implementation run using the synthesis porperties.

 

[dhanya22]

ads-ee
Can you please explain a little , as I have not worked with generic setting

 

[sharath666]

VHDL -> generics
Verilog -> parameters
Read up on this...

 

[ads-ee]

Add a generic/parameter to the code for the bit widths of the input/outputs of the adder. Then set the generic/parameter from the ISE synthesis properties panel (assuming ISE as you did not specify)


The syntax is like this: {parameter_name_1=0 parameter_name2=1}

{} around the entire thinig, no spaces around the "=" and spaces between the name/value pairs. See the guidelines and examples on page 330