Elephantus
Junior Member level 3
xilinx fifo
I am using a synchronous common clock fifo in my design based on a Xilinx spartan 2 fpga.
I've synthesized the FIFO using Xilinx coregen from ISE 7.1 as a 16-bit wide, 32 words deep fifo implemented using a block ram, with only the minimum set of IO ports (wr_en, rd_en, clk, empty, full,din,dout,clk,rst).
The design worked well in the simulation, however the implementation of the design in the FPGA would halt in a random moment. Using chipscope i detected that in a point of time, the fifo activates both "full" and "empty" flags.
Normally, the fifo raises both flags in the reset state, however the external reset pin of the design (and the internal net) is deactivated at the time when the fifo asserts both "full" and "empty" flags. After that event, which lasts for cca. 5 periods of clk, the fifo holds "empty" always asserted, and asserts full when the fifo is filled, resulting in a deadlock of the system (the logic that reads from the fifo never reads anything, given that the fifo indicates empty state).
Has anyone encountered such a problem when using coregen generated fifos (and solved it, probably)?
I would appreciate any help.
Thanks.
I am using a synchronous common clock fifo in my design based on a Xilinx spartan 2 fpga.
I've synthesized the FIFO using Xilinx coregen from ISE 7.1 as a 16-bit wide, 32 words deep fifo implemented using a block ram, with only the minimum set of IO ports (wr_en, rd_en, clk, empty, full,din,dout,clk,rst).
The design worked well in the simulation, however the implementation of the design in the FPGA would halt in a random moment. Using chipscope i detected that in a point of time, the fifo activates both "full" and "empty" flags.
Normally, the fifo raises both flags in the reset state, however the external reset pin of the design (and the internal net) is deactivated at the time when the fifo asserts both "full" and "empty" flags. After that event, which lasts for cca. 5 periods of clk, the fifo holds "empty" always asserted, and asserts full when the fifo is filled, resulting in a deadlock of the system (the logic that reads from the fifo never reads anything, given that the fifo indicates empty state).
Has anyone encountered such a problem when using coregen generated fifos (and solved it, probably)?
I would appreciate any help.
Thanks.