Xilinx Coregen fifo generator problem

[Elephantus]

xilinx fifo

I am using a synchronous common clock fifo in my design based on a Xilinx spartan 2 fpga.

I've synthesized the FIFO using Xilinx coregen from ISE 7.1 as a 16-bit wide, 32 words deep fifo implemented using a block ram, with only the minimum set of IO ports (wr_en, rd_en, clk, empty, full,din,dout,clk,rst).

The design worked well in the simulation, however the implementation of the design in the FPGA would halt in a random moment. Using chipscope i detected that in a point of time, the fifo activates both "full" and "empty" flags.

Normally, the fifo raises both flags in the reset state, however the external reset pin of the design (and the internal net) is deactivated at the time when the fifo asserts both "full" and "empty" flags. After that event, which lasts for cca. 5 periods of clk, the fifo holds "empty" always asserted, and asserts full when the fifo is filled, resulting in a deadlock of the system (the logic that reads from the fifo never reads anything, given that the fifo indicates empty state).

Has anyone encountered such a problem when using coregen generated fifos (and solved it, probably)?

I would appreciate any help.
Thanks.

 

[echo47]

fifo generator xilinx

I saw bad things like that when I violated the FIFO timing by applying an external clock that was occasionally fuzzy/noisy (when I disconnected the cable). The coregen FIFO got stuck in an confused state, and would not recover unless reset.

My solutions:
1. Clean up the fuzzy/noisy clock.
2. Stop using Xilinx corgen parts. Most of them are mediocre quality. I can do better.

 

[soccer]

xilinx fifo reset

try www.opencore.com for your requirment, i use it usually.

 

[syedahmar]

fifo xilinx coregen problems

I have used xilinx core generator and i implemented fifo on spartan 3 device. Since the depth was 1024 in my design, i never filled it during testing. However i faced another problem initially while trying to use the core generator and what i did was that i updated my core generator software and it solved my problem. Try to update your core generator, it may help .....And if it doesn't, then write your own code in HDL. It sure is a better idea from learning and getting more skills perspective.....best of luck....