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XC9572 -Binary counter

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shell_inspector

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xc9572 schematic

Hello,
I am working with a XC9572-pc44 CPLD using the free Webpack ISE7.1.1 For some unconown reason the simply implemented 8 bit binary counter ("hello world") won't do it's thing. Instead of having each bit deviding clock's frequency by 2, the frequency of each bit is clock/2. In addition the bits are jiggling in phase like:: 10101010010101011010101...
The clock is slow, about 1kHz, the Clear and CLk look fine on the Scope. Here's the source which is straight from the book. I suspect the ISE7.1.1 is buggy.
========
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity counter is
Port (
CLEAR: in std_logic;
Q5: out std_logic_vector(7 downto 0);
CLK : in std_logic);
end counter;

architecture Behavioral of counter is

signal Q5_IN : std_logic_vector(7 downto 0); -- Defines internal signals
begin
Q5 <= Q5_IN; -- Set output
process(CLEAR, CLK) begin
if CLEAR='1' then -- Clear counter ?
Q5_IN <= "00000000"; -- Yes. Clear counter
elsif CLK='1' and CLK'event then -- Clock rising edge ?

if Q5_IN=128 then -- Yes. Count = 4 ?
Q5_IN <= "00000000"; -- Yes. Clear counter
else -- No
Q5_IN <= Q5_IN + '1'; -- Count-up
end if;

end if;
end process;
end Behavioral;
 

echo47

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shell_inspector

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source xilinx unlooper

Thanks echo, updating to version 8.1 did the trick!
 

simce

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eagle xc9572

Hi shell_inspector,
I'm about to begin learning how to use CPLD devieces and i decided to use XC9572 to enter into this world. I have XC9572 chip but i can not find any schematic how to make my own board. Can you please give me schematic of your board and simple example you menitioned here so i can make my first step.
 

bubu321

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bit w xc9572

@ simce

hi,
- look at this page http://www.seng.de/dlk51_.html
- CPLD demo source code, CPLD Jedec file
- Manual dlk51 including schematic, brochures and readme-file
- EAGLE files, board schematic and library.
- look also to unlooper board, it's simly
 

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