module divby_11_22(clk, by_11, by_22);
input clk;
output by_11;
output by_22;
reg [4:0] counter;
always @(posedge clk)
begin
if (counter == 5'd21) counter <= 5'd0;
else counter <= counter + 5'd1;
// divide-by-11 clock is high for 5, low for 6
if ((counter == 5'd0)||(counter == 5'd11) by_11 <= 1'b1;
if (counter == 5'd5) || (counter == 5'd16)) by_11 <= 1'b0;
// divide-by-22 is 11 high, 11 low
if (counter == 5'd0) by_22 <= 1'b1;
if (counter == 5'd11) by_22 <= 1'b0;
end
endmodule