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Xc9500xl ucf File Problems

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priestnot

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First of all thanks for your time to read this post...

OK I am trying to implement a simple project to test a XC9500XL board with a Xilinx XC2C256 CPLD.

I have managed to create a .ucf file with the Reference Manual page 6.

Code:
NET	"SYSCLK"	LOC =	"38";

NET	"A4"	LOC =	"43";
NET	"A5"	LOC =	"42";
NET	"A6"	LOC =	"41";
NET	"A7"	LOC =	"39";
NET	"A8"	LOC =	"40";
NET	"A10"	LOC =	"34";
NET	"A11"	LOC =	"35";
NET	"A12"	LOC =	"33";
NET	"A13"	LOC =	"32";
NET	"A14"	LOC =	"31";
NET	"A15"	LOC =	"30";
NET	"A16"	LOC =	"28";
NET	"A17"	LOC =	"26";
NET	"A18"	LOC =	"25";
NET	"A19"	LOC =	"24";
NET	"A20"	LOC =	"23";
NET	"A21"	LOC =	"22";
NET	"A22"	LOC =	"21";
NET	"A23"	LOC =	"20";
NET	"A24"	LOC =	"19";
NET	"A25"	LOC =	"18";
NET	"A26"	LOC =	"17";
NET	"A27"	LOC =	"16";
NET	"A28"	LOC =	"15";
NET	"A29"	LOC =	"14";
NET	"A30"	LOC =	"13";
NET	"A31"	LOC =	"12";
NET	"A32"	LOC =	"11";
NET	"A33"	LOC =	"10";
NET	"A34"	LOC =	"9";
NET	"A35"	LOC =	"7";
NET	"A36"	LOC =	"6";
NET	"A37"	LOC =	"5";
NET	"A38"	LOC =	"4";
NET	"A39"	LOC =	"3";
NET	"A40"	LOC =	"2";

NET	"B5"	LOC =	"142";
NET	"B6"	LOC =	"140";
NET	"B7"	LOC =	"139";
NET	"B8"	LOC =	"138";
NET	"B9"	LOC =	"137";
NET	"B10"	LOC =	"136";
NET	"B11"	LOC =	"135";
NET	"B12"	LOC =	"134";
NET	"B13"	LOC =	"133";
NET	"B14"	LOC =	"132";
NET	"B15"	LOC =	"131";
NET	"B16"	LOC =	"130";
NET	"B17"	LOC =	"129";
NET	"B18"	LOC =	"128";
NET	"B19"	LOC =	"126";
NET	"B20"	LOC =	"125";
NET	"B21"	LOC =	"124";
NET	"B22"	LOC =	"121";
NET	"B23"	LOC =	"120";
NET	"B24"	LOC =	"119";
NET	"B25"	LOC =	"118";
NET	"B26"	LOC =	"117";
NET	"B27"	LOC =	"116";
NET	"B28"	LOC =	"115";
NET	"B29"	LOC =	"114";
NET	"B30"	LOC =	"113";
NET	"B31"	LOC =	"112";
NET	"B32"	LOC =	"111";
NET	"B33"	LOC =	"110";
NET	"B34"	LOC =	"107";
NET	"B35"	LOC =	"106";
NET	"B36"	LOC =	"105";
NET	"B37"	LOC =	"104";
NET	"B38"	LOC =	"103";
NET	"B39"	LOC =	"102";
NET	"B40"	LOC =	"101";

NET	"D12"	LOC =	"80";
NET	"D13"	LOC =	"79";
NET	"D14"	LOC =	"78";
NET	"D15"	LOC =	"77";
NET	"D16"	LOC =	"76";
NET	"D17"	LOC =	"75";
NET	"D18"	LOC =	"74";
NET	"D19"	LOC =	"71";
NET	"D20"	LOC =	"70";
NET	"D21"	LOC =	"69";
NET	"D22"	LOC =	"68";
NET	"D23"	LOC =	"66";
NET	"D24"	LOC =	"64";
NET	"D25"	LOC =	"61";
NET	"D26"	LOC =	"60";
NET	"D27"	LOC =	"59";
NET	"D28"	LOC =	"58";
NET	"D29"	LOC =	"57";
NET	"D30"	LOC =	"56";
NET	"D31"	LOC =	"54";
NET	"D32"	LOC =	"53";
NET	"D33"	LOC =	"52";
NET	"D34"	LOC =	"51";
NET	"D35"	LOC =	"50";
NET	"D36"	LOC =	"49";
NET	"D37"	LOC =	"48";
NET	"D38"	LOC =	"46";
NET	"D39"	LOC =	"45";
NET	"D40"	LOC =	"44";


NET	"LD2"	LOC =	"92";

NET	"BTN1"	LOC =	"143";

and then i created a toplevel file to interact with the IO:

Code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: FEUP/DEEC
// Engineer: Eduardo Sousa
// 
// Create Date:    10:13:45 05/19/2011 
// Design Name: 
// Module Name:    xc2c256_toplevel 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: XC9500XL toplevel for the xc2c256
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module xc2c256_toplevel
(
	// XC9500XL (xc2c256) toplevel FILE		
	//[Net pin name],
	
	// System Clock	
	SYSCLK,
	
	//BTN
	BTN1,
	
	// LED2
	LD2,
	
	// Expansion connector A:	
	A4,
	A5,
	A6,
	A7,
	A8,
	A10,
	A11,
	A12,
	A13,
	A14,
	A15,
	A16,
	A17,
	A18,
	A19,
	A20,
	A21,
	A22,
	A23,
	A24,
	A25,
	A26,
	A27,
	A28,
	A29,
	A30,
	A31,
	A32,
	A33,
	A34,
	A35,
	A36,
	A37,
	A38,
	A39,
	A40,

	// Expansion connector B:
	B5,
	B6,
	B7,
	B8,
	B9,
	B10,
	B11,
	B12,
	B13,
	B14,
	B15,
	B16,
	B17,
	B18,
	B19,
	B20,
	B21,
	B22,
	B23,
	B24,
	B25,
	B26,
	B27,
	B28,
	B29,
	B30,
	B31,
	B32,
	B33,
	B34,
	B35,
	B36,
	B37,
	B38,
	B39,
	B40,


	// Expansion connector C:
	D12,
	D13,
	D14,
	D15,
	D16,
	D17,
	D18,
	D19,
	D20,
	D21,
	D22,
	D23,
	D24,
	D25,
	D26,
	D27,
	D28,
	D29,
	D30,
	D31,
	D32,
	D33,
	D34,
	D35,
	D36,
	D37,
	D38,
	D39,
	D40,
);

// System Clockinput	
input	SYSCLK;

// BTN
input	BTN1;
// LED2
output	LD2;

//-----------------------------------------------------------------------------------
//
// Interface signals of expansion connector A
// Pin direction must be modified for each application
//

//A1 	GND
//A2	VU
//A3	VDD33
input	A4;
input	A5;
input	A6;
input	A7;
input	A8;
//A9	XLCLK
input	A10;
input	A11;
input	A12;
input	A13;
input	A14;
input	A15;
input	A16;
input	A17;
input	A18;
input	A19;
input	A20;
input	A21;
input	A22;
input	A23;
input	A24;
input	A25;
input	A26;
input	A27;
input	A28;
input	A29;
input	A30;
input	A31;
input	A32;
input	A33;
input	A34;
input	A35;
input	A36;
input	A37;
input	A38;
input	A39;
input	A40;

//-----------------------------------------------------------------------------------
//
// Interface signals of expansion connector B
// Pin direction must be modified for each application
//

//A1 	GND
//A2	VU
//A3	VDD33
//A4	BTN1
input	B5;
input	B6;
input	B7;
input	B8;
input	B9;
input	B10;
input	B11;
input	B12;
input	B13;
input	B14;
input	B15;
input	B16;
input	B17;
input	B18;
input	B19;
input	B20;
input	B21;
input	B22;
input	B23;
input	B24;
input	B25;
input	B26;
input	B27;
input	B28;
input	B29;
input	B30;
input	B31;
input	B32;
input	B33;
input	B34;
input	B35;
input	B36;
input	B37;
input	B38;
input	B39;
input	B40;


//-----------------------------------------------------------------------------------
//
// Interface signals of expansion connector D
// Pin direction must be modified for each application
//

//D1	GND
//D2	VU
//D3	VDD33
//NOT	D4;
//D5	L5
//NOT	D6;
//NOT	D7;
//NOT	D8;
//NOT	D9;
//NOT	D10;
//NOT	D11;
input	D12;
input	D13;
input	D14;
input	D15;
input	D16;
input	D17;
input	D18;
input	D19;
input	D20;
input	D21;
input	D22;
input	D23;
input	D24;
input	D25;
input	D26;
input	D27;
input	D28;
input	D29;
input	D30;
input	D31;
input	D32;
input	D33;
input	D34;
input	D35;
input	D36;
output	D37;
output	D38;
input	D39;
output	D40;

//Turn BTN1 into reset button
assign SYSRST=BTN1;

//teste para apagar
assign D40=1'b0;
assign D38=1'b1;

assign D37 = D36;

endmodule


As you can see all i have done was to crete a module with all the IO pins Clock and a Button wich i connected like this:
Code:
//Turn BTN1 into reset button
assign SYSRST=BTN1;

//teste para apagar
assign D40=1'b0;
assign D38=1'b1;

assign D37 = D36;

Whem i implement the design i get this error:
Code:
ERROR:Cpld:832 - 'D37' is assigned to an invalid location ('48') for this
   device.  This will prevent the design from fitting on the current device.
   'D37' must be reassigned before attempting a re-fit.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.

Can some one tell me what the problem is? Does it mean i cannot connect a IO to another directly?
Thanks for all the help....

---------- Post added at 19:57 ---------- Previous post was at 19:26 ----------

Alredy solved
 

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