# X+HDL Verilog2Vhdl error with 'wire'

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#### TurboPC

##### Advanced Member level 4
I am using X+HDL to convert a verilog module to vhdl. I get a syntax error on the keyword 'wire'. What should I do? Is there another syntax keyword I should use? Note: I am not very familiar with verilog.

Disclaimer: I have seen a mention of this bug on Elektroda before, but I can't find it anymore. Thanks!

#### TurboPC

##### Advanced Member level 4
Oups! Bug is coming from undef statement

The error is coming from the line before the wire statement:

'undef toto
ifdef toto
reg [5 : 0] a,b,c,d;
else
wire [5 : 0] a,b,c,d;
`endif

Just commenting line <'undef toto > solves the problem. However, xhdl repost an error at the end of the file. I have to coment properly all the 'ifdef', 'else' and 'endif statements to correct the bug.

Any other workaround?

Regards!

#### ngisst

##### Newbie level 2
you have missed ";" in the end of line...

wire [5 : 0] a,b,c,d ;

#### TurboPC

##### Advanced Member level 4
Thanks for the ';' comment, but it 's a typo when I copied the example to elektroda...

My question still stands...

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